Session Timeout

Your session is about to expire. Do you want to extend the session?

00:

59

Extend My Session

Custom Meta Tags

Programmable logic HB2 Abacus

Programmable logic

Design Hub

Search Reference Designs

Subnav

Category Attributes

Browse Designs By

Aerospace & defense ()

Category Attributes

Programmable logic Reference Designs

Programmable logic components are used to build reconfigurable digital circuits, shortening development cycles for manufacturers, and helping them get their product to the market faster. Explore our articles and information on the latest in CPLDs, FP

Reference Design Block Diagram of AI Camera and Voice Recognition Solution based on Renesas Solution

AI Camera and Voice Recognition Solution based on Renesas Solution

Reference Design of a smart motor driving circuit, using the RA6T2 MCU and RAA227063 3-phase smart driver for processing speed and power efficiency to address traction of the motors

Reference Design Block Diagram of AIoT Application Development Kit based on ISSI's T31-INDUS Solution

AIoT Application Development Kit based on ISSI's T31-INDUS Solution

This development kit consists of development boards (core module, WIFI module, and sensor board), an operating system, and an SDK package.

Reference Design Block Diagram of AMD Artix 7 Power Tree based on onsemi Solution

AMD Artix 7 Power Tree based on onsemi Solution

The AMD Artix 7 Power Tree is a power management solution that provides the necessary power rails to the FPGA using onsemi's key power devices.

Reference Design Block Diagram of AMD Artix 7 Starter Recipe

AMD Artix 7 Starter Recipe

Starter Recipe for the AMD Artix-7 family of cost and transceiver optimized FPGAs.

Reference Design Block Diagram of AMD Artix UltraScale+ (AU10P-AU15P) Power Tree based on onsemi Solution

AMD Artix UltraScale+ (AU10P-AU15P) Power Tree based on onsemi Solution

The AMD Artix UltraScale+ (AU10P/AU15P) Power Tree is a power management solution for the Artix UltraScale+ FPGA Family using onsemi's key power devices.

Reference Design Block Diagram of AMD Artix UltraScale+ Starter Recipe

AMD Artix UltraScale+ Starter Recipe

Artix UltraScale+ devices are the industry only cost-optimized FPGAs based on an advanced, production-proven 16nm architecture for best-in-class performance....

Reference Design Block Diagram of AMD Kintex UltraScale (KU035-KU075) Power Tree based on onsemi Solution

AMD Kintex UltraScale (KU035-KU075) Power Tree based on onsemi Solution

The AMD Kintex UltraScale (KU035/KU076) Power Tree is a power management solution for the Kintex UltraScale FPGAs using onsemi's key power devices.

Reference Design Block Diagram of AMD Kintex UltraScale (KU100) Power Tree based on onsemi Solution

AMD Kintex UltraScale (KU100) Power Tree based on onsemi Solution

The AMD Kintex UltraScale (KU100) Power Tree is a power management solution for the Kintex UltraScale FPGAs using onsemi's key power devices.

Reference Design Block Diagram of AMD Kintex UltraScale+ Starter Recipe

AMD Kintex UltraScale+ Starter Recipe

Kintex UltraScale+ devices provide the best price/performance/watt balance in a FinFET node.

Reference Design Block Diagram of AMD Spartan 7 Power Tree based on onsemi Solution

AMD Spartan 7 Power Tree based on onsemi Solution

The AMD Spartan 7 Power Tree is a power management solution that provides the necessary power rails to the FPGA using onsemi's key power devices.

Reference Design Block Diagram of AMD Spartan 7 Starter Recipe

AMD Spartan 7 Starter Recipe

Spartan-7 devices offer the best in class performance per watt, along with small form factor packaging to meet the most stringent requirements

Reference Design Block Diagram of AMD Versal AI Starter Recipe

AMD Versal AI Starter Recipe

Starter Recipe for the AMD Versal AI family of ACAP devices.

Reference Design Block Diagram of AMD Versal Premium Starter Recipe

AMD Versal Premium Starter Recipe

Starter Recipe for AMD Versal Premium family of ACAP devices.

Reference Design Block Diagram of AMD Versal Prime Starter Recipe

AMD Versal Prime Starter Recipe

Starter Recipe for AMD's Versal Prime family of ACAP devices.

Reference Design Block Diagram of AMD Virtex UltraScale (VU080-VU095) Power Tree based on onsemi Solution

AMD Virtex UltraScale (VU080-VU095) Power Tree based on onsemi Solution

The AMD Virtex UltraScale (VU080/VU095) Power Tree is a power management solution for the Virtex UltraScale FPGAs using onsemi's key power devices.

Reference Design Block Diagram of AMD Virtex UltraScale+ (VU11P-VU13P) Power Tree based on onsemi Solution

AMD Virtex UltraScale+ (VU11P-VU13P) Power Tree based on onsemi Solution

The AMD Virtex UltraScale+ (VU11P/VU13P) power solution is a general-purpose power tree for the Virtex UltraScale+ series of FPGAs using onsemi's key power devices.

Reference Design Block Diagram of AMD Virtex UltraScale+ (VU31P-VU37P) Power Tree based on onsemi Solution

AMD Virtex UltraScale+ (VU31P-VU37P) Power Tree based on onsemi Solution

The AMD Virtex UltraScale+ (VU31P/VU37P) power solution is a general-purpose power tree for the Virtex UltraScale+ series of FPGAs using onsemi's key power devices.

Reference Design Block Diagram of AMD Virtex UltraScale+ Power Tree based on onsemi Solution

AMD Virtex UltraScale+ Power Tree based on onsemi Solution

The AMD Virtex UltraScale+ power solution is a general-purpose power tree for the Virtex UltraScale+ series of FPGAs using onsemi's key power devices.

Reference Design Block Diagram of AMD Virtex UltraScale+ Starter Recipe

AMD Virtex UltraScale+ Starter Recipe

Virtex UltraScale+ devices provide the highest performance and integration capabilities in a 14nm/16nm FinFET node

Reference Design Block Diagram of AMD Zynq 7000 Power Tree based on onsemi Solution

AMD Zynq 7000 Power Tree based on onsemi Solution

The AMD Zynq 7000 Power Tree is a power management solution that provides the necessary power rails to the FPGA using onsemi's key power devices.

Reference Design Block Diagram of AMD Zynq 7000 Starter Recipe

AMD Zynq 7000 Starter Recipe

The Zynq-7000 SoC family integrates the software programmability of an ARM-based processor with the hardware programmability of an FPGA,...

Reference Design Block Diagram of AMD Zynq UltraScale+ MPSoC Power Supply based on Renesas Solution

AMD Zynq UltraScale+ MPSoC Power Supply based on Renesas Solution

Provides the perfect development environment for evaluating the unprecedented levels of performance, system integration and bandwidth provided by Virtex UltraScale devices.

Reference Design Block Diagram of AMD Zynq UltraScale+ MPSoC Starter Recipe

AMD Zynq UltraScale+ MPSoC Starter Recipe

Zynq UltraScale+ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics.

Reference Design Block Diagram of AMD Zynq UltraScale+ Power Tree based on onsemi Solution

AMD Zynq UltraScale+ Power Tree based on onsemi Solution

The AMD Zynq UltraScale+ Power Tree is a power supply configuration designed for the Zynq UltraScale+ MPSoC family using onsemi's key power devices.

Reference Design Block Diagram of AMD Zynq UltraScale+ RFSoC Starter Recipe

AMD Zynq UltraScale+ RFSoC Starter Recipe

The monolithic integration of direct RF-sampling data converters onto an adaptive SoC eliminates the need for external data converters, enabling a flexible solution with up to 50% reduced power...

Reference Design Block Diagram of Avnet Ultra96-V2 Development Board Chipdown Block Diagram

Avnet Ultra96-V2 Development Board Chipdown Block Diagram

Chipdown - The Ultra96-V2 updates and refreshes the Ultra96 product that was released in 2018. Like Ultra96, the Ultra96-V2 is an Arm-based, AMD Zynq UltraScale+ MPSoC development board.

Reference Design Block Diagram of Avnet ZUBoard 1CG Development Board

Avnet ZUBoard 1CG Development Board

The ZUBoard 1CG provides the flexibility and versatility for engineers to experiment with and learn the MD-AMD Zynq UltraScale+ architecture.

Reference Design Block Diagram of BLDC Traction Motor Drive based on Renesas Solution

BLDC Traction Motor Drive based on Renesas Solution

Reference Design of a smart motor driving circuit, using the RA6T2 MCU and RAA227063 3-phase smart driver for processing speed and power efficiency to address traction of the motors

Reference Design Block Diagram of Clocking for PolarFire FPGAs based on Microchip Solution

Clocking for PolarFire FPGAs based on Microchip Solution

Fully designed, tested and validated clocking solution to work with PolarFire FPGAs and SoCs.

Reference Design Block Diagram of DC Motor Anomaly Detection System based on Arduino Solution

DC Motor Anomaly Detection System based on Arduino Solution

This Arduino-powered solution implements an energy monitoring-based anomaly detection system using a current sensor and machine learning models running on edge devices.

First 1 2 Last Results Per Page: 30 60 90 all

Complementary Content

${loading}