Tech Day Italy: Compute, Adapt, Accelerate
26 Jun 2024 - 26 Jun 2024
Italy, Milano
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Avnet Silica, AMD e partner presentano una giornata di approfondimento tecnico
Esplora gli ultimi progressi nell'ampio portfolio prodotti di AMD e scopri prodotti e soluzioni complementari dagli altri nostri partner globali.
Avrai l'opportunità di apprendere dalle menti più brillanti del settore attraverso sessioni tecniche interattive condotte da ingegneri di AMD, Avnet Silica e alcuni partner selezionati.
Inoltre, potrai vincere fantastici premi! Tutti i partecipanti verranno inseriti in un'estrazione a premi per avere la possibilità di vincere alcuni tra gli ultimi kit di sviluppo e schede AMD.
Non perdere questa straordinaria opportunità di apprendimento e networking in occasione di questo evento innovativo che promette di ridefinire il tuo approccio al design.
Non vediamo l'ora di incontrarti!
Data e ora
- 26 giugno 2024 - 9.00-17.30 (8.30 registrazione e accoglienza)
Luogo
- Gran Visconti Palace, Milano, Italy
Agenda
Time |
Track 1 (x86 & Power) |
Track 2 (Software, Tools & AI) |
Track 3 (FPGA & Markets) |
08:30-09:00 |
Registration & Welcome |
09:00-09:15 |
Keynote (Alberto Fusaschi, AMD) |
09:20-10:10 |
Discover the AMD x86 Embedded Landscape & Roadmap
(Fabio Caccamo, AMD) |
Discover Vitis AI
(Sophie Lemaire, AMD) |
Discover the AMD FPGA & SoC Technology Landscape
(Massimo Bertoli, Avnet Silica) |
10:10-10:15 |
Break |
10:15-11:05 |
Kontron cutting-edge technology based on AMD embedded solutions
(Thomas Stanik, Kontron) |
Real world Video Application with Gstreamer Part I
(Stefano Tabanelli, Avnet Silica) |
Latest AMD technologies
(Maxime Rocca, AMD) |
11:05-11:30 |
Coffee Break & Marketplace |
11:30-12:20 |
The Embedded World Powered by Advantech/ AMD solutions
(Marco Pavesi, Advantech) |
Real world Video Application with Gstreamer Part II
(Stefano Tabanelli, Avnet Silica) |
A&D and Space Update
(Maxime Rocca, AMD) |
12:20-13:55 |
Lunch & Marketplace |
13:55-14:45 |
Multiphase COT Power Modules for Powering FPGAs
(Tomas Hudson, MPS) |
Adaptable Intelligent (AI) Engine Architecture and Programming
(Emanuele Renzi, Avnet Silica) |
Support from AMD safety package in the certification process
(Fabio Caccamo, AMD) |
14:45-14:50 |
Break |
14:50-15:40 |
Clocking of FPGA, SerDes and High Speed Interfaces with very low jitter Oscillators and PLL based Jitter Cleaner solutions
(Pierre Delloye, SiTime) |
Microsoft Embedded
(Martin Grossen, Avnet Silica) |
Designing with high-speed interfaces, debugging techniques and design considerations
(Francesco Contu, Avnet Silica) |
15:40-16:00 |
Coffee Break & Marketplace |
16:00-16:50 |
Timing & Power solutions for your Space and Industrial FPGA design
(Michele Pergola & Silvia Sinibaldi, Renesas) |
Design Considerations and Techniques Using the Vivado Design Suite
(Andrea Borga, Avnet Silica) |
RF_SOC advanced usage: multi channel and multi chip synchronization
(Francesco Contu, Avnet Silica) |
16:50-17:30 |
Wrap-up & Prize Draw & Open Talks |
Partners
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Registration
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AMD Tech Day Italy | Avnet Silica