When GaN is too fast for your application, consider SiC instead | Avnet Silica

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When GaN is too fast for your application, consider SiC instead | Avnet Silica

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When GaN is too fast for your application, consider SiC instead

Nishant Nishant
Wide bandgap semiconductor material in its raw form
Wide bandgap semiconductors offer huge advantages in many power circuits, but you need to choose according to your application’s needs.

In the world of semiconductor power switches, there is a belief that faster is better. Right now, Gallium Nitride (GaN) devices are the front-runners, with switching rates of over 100V/ns and 1A/ns. At these speeds, slewing from zero to, say, 400V in a typical power converter application takes just a few nanoseconds.

If the topology used is hard switched with volts and amps momentarily present together on transitions, the overlap and dissipation are minimized. This enables higher frequency operation with low dynamic loss in the semiconductors, even with the increased number of switching transitions at MHz rates. In a hard-switched converter, the absence of reverse recovery losses in a GaN HEMT cell is also a major plus.

However, high voltage and current edge rates cause other problems. The slightest inductance causes ringing and overshoot. Using the familiar E=-L.di/dt equation, 1V could be generated from 1nH at an edge rate of 1A/ns. It only takes around 1mm of tracking to reach this value of inductance.

If this is a GaN-source connection and is common to the gate drive loop, that 1V spike will be injected into the gate, in opposition to the drive voltage. With the low threshold voltage of GaN being at around 1.5V, this presents the risk of phantom turn-on and device damage.

Connections from the switch to the load could easily be 100x longer in a high-power system, with a 100V overshoot, or more, induced on the drain. As GaN has no avalanche mechanism, these excess voltages can be fatal.

Similarly, there can be a high voltage edge rate, dV/dt, on the drain injecting current into the gate through the Miller capacitance CGD, and although low for a typical GaN HEMT cell at perhaps 2pF, this would still force 200mA back into the gate driver with 100V/ns applied, attenuated somewhat by gate-source capacitance. Again, the action is to oppose the gate drive. At the same time, device and circuit capacitances ring with the induced voltages and currents, producing EMI with spurs at tens or hundreds of MHz, which can bypass filters and be problematic.

Miller effect in GaN power transistors

schematic

High di/dt and dV/dt in GaN HEMT cells can couple back into the gate drive loop.

In practice, GaN circuits are typically slowed down

The issues are well known, and engineers will typically slow down switching rates using a variety of methods. Adding series gate resistance is one simpler option, perhaps with different on and off values through a steering diode. Adding anything in series with the gate inevitably adds inductance as well though, so overshoot and ringing can again occur.

A GaN HEMT cell does not have an insulated gate like a SiC MOSFET and features a Schottky diode across its gate, with low-level current injected and extracted to turn the device on and off. Some schemes tailor the exact shape of the current in picosecond timescales to control overshoot. This is effective but very complex and practically only implemented in GaN devices with integrated drivers, which are relatively expensive.

two schematics

These are equivalent circuits of a GaN HEMT cell (left) and SiC MOSFET (right).

Another possibility is to live with the effects and mitigate them. For example, a negative off-state gate drive helps avoid phantom turn-on. For sure, a Kelvin connection should be used for the source connection to the gate drive loop to minimize common inductance. Snubbers at the drain can even be used to tame and shape the drain voltage to limit and damp overshoots. All this adds cost and complexity, however. In any case, careful board layout is necessary using RF techniques to minimize stray effects.

Why does GaN switch so fast?

Running GaN with fast edge rates is necessary to minimize losses at high frequency, but is it necessary or even desirable to go so fast? Contrary to common lore, running a converter at high frequency reduces efficiency, needing bigger and heavier heat sinking, all else being equal. The primary reason to do it is to make other components smaller, mainly magnetics, as fewer turns are needed for the same core flux density, which is limited to a saturation value.

The hope is that, in turn, copper losses reduce. But if you also try to make the core smaller, more turns are needed for the same flux density and gains are reversed. At the same time, a given flux density produces exponentially higher core losses as frequency increases, so either the turns must increase again, or the core made larger to decrease flux density to compensate.

In practice, the benefits in magnetics start to disappear in the MHz range in power conversion. In theory, at the highest frequencies, a core is not needed and there would be no flux density limit, but then coupling is poor and the consequent high leakage inductance and low magnetizing inductance present further problems. If the magnetic element is a transformer with safety isolation, the size is often ultimately set by statutory creepage and clearance distances anyway.

If the load is a motor such as in a traction inverter, high frequencies have very little benefit and these applications typically run at sub 20kHz, even with Si or SiC MOSFETs. Many power designers work to reduce switching frequency where possible for these reasons and setting it to be a little less than 150kHz also keeps the fundamental below the starting frequency for common European standards (abbreviated EN, from the German name Europäische Norm ("European Norm")) and Federal Communications Commission (FCC) EMC compliance limit lines.

SiC can make sense in many applications

Using SiC MOSFETs at relatively low frequencies instead of GaN can make sense as dynamic losses are low anyway, especially if the circuit is a resonant type. In this case, the absence of reverse recovery losses in GaN is also not of value. Both GaN and SiC will have higher and approximately equal body conduction losses in reverse compared with a Si-MOSFET. SiC will also need some effort to slow down and control edge rates – it is still much faster than silicon – but it will be easier to tame.

The voltage limit of around 650V for GaN is also a practical limitation. Stacked or multilevel arrangements can allow operation to higher levels, but the cost and complexity spiral. Weigh this against the SiC MOSFET advantages of a simpler and more noise-immune gate drive, a robust avalanche rating, and currently lower cost and better availability, and SiC continues to keep its place as a contender in power conversion applications.

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Nishant Nishant
Avnet Staff

We use Avnet Staff as a collective byline when our team of editors and writers collaborate on the co...

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