New Product Introduction

Renesas GreenPAK™ Configurable Mixed-Signal ICs

Renesas GreenPAK™ SLG46826 and SLG46824 are the first CMICS to support in-system programming, are available in a 2.0 x 3.0 mm 20pin STQFN package and are streamling the development process.

Dialog Semi - GreenPAK component image

The SLG46826 and the SLG46824 are the market’s first CMICs that support in-system programming using a simple I²C serial interface. This streamlines the development process as it allows the installation of an un-programmed GreenPAK on the PCB, and supports programming of the Non-Volatile Memory (NVM) in-system, for easy system checkout. This flexibility is also beneficial in the production environment, as it is easy to modify the configuration or add functionality to these devices by programming the non-volatile memory on the production line. The NVM on this device is specified for 1,000 erase/write cycles.

Available in a 2.0 x 3.0 mm 20-pin STQFN package, both CMICs are equipped with low power consumption analog and digital resources like analog comparators (ACMPs), an internal voltage reference, power-on reset, and more advanced digital resources, like multi-function macro-cells. Running the low power analog comparators with the internal low power voltage reference consumes just 2.5 µA typical for two ACMPs that are continuously monitoring external signals.
 

Target applications

Consumer electronics Commercial and industrial electronics
  • IoT Devices, Wearables, Smart Tags
  • Smartphones, Tablets, Notebooks
  • PCs and PC peripherals
  • Headphones, Headsets
  • Smart Building, Smart TV, Set Top Box
  • Servers
  • Embedded computing
  • Medical devices

 

  • SLG46824
  • SLG46826

17-GPIO, 2 ACMPs, I2C, 19 LUTs (max.), 8 CNT/DLY (max.), 17 DFF/LATCH (max.) and other Macrocells

The SLG46824 provides a small, low power component for commonly used mixed-signal functions. The user creates the circuit design by programming the multiple time Non-Volatile Memory (NVM) to configure the interconnect logic, the IOs and the macrocells of the SLG46824. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit.
 

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Macrocells overview
 

  • Two Low Power General Purpose Rail-to-Rail Analog Comparators (ACMPxL)
  • One Voltage Reference (Vref)
  • Eleven Combination Function Macrocells
    • Three Selectable DFF/Latch or 2-bit LUTs
    • One Selectable Programmable Pattern Generator or 2-bit LUT
    • Six Selectable DFF/Latch or 3-bit LUTs
    • One Selectable Pipe Delay or Ripple Counter or 3-bit LUT;
  • Eight Multi-Function Macrocells
    • Seven Selectable DFF/Latch or 3-bit LUTs + 8-bit Delay/Counters
    • One Selectable DFF/Latch or 4-bit LUT + 16-bit Delay/Counter
  • Serial Communications
    • I²C Protocol Interface
  • Programmable Delay with Edge Detector Output
  • Deglitch Filter with Edge Detector;
  • Three Oscillators (OSC)
    • 2.048 kHz Oscillator
    • 2.048 MHz Oscillator
    • 25 MHz Oscillator
  • Power On Reset (POR)

 

17-GPIO, 4 ACMPs, I2C, 19 LUTs (max.), 8 CNT/DLY (max.), 17 DFF/LATCH (max.) and other Macrocells

The SLG46826 provides a small, low power component for commonly used mixed-signal functions. The user creates the circuit design by programming the multiple time Non-Volatile Memory (NVM) to configure the interconnect logic, the IOs and the macrocells of the SLG46826. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit.
 

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Macrocells overview
 

  • Two High Speed General Purpose Rail-to-Rail Analog Comparators (ACMPxH)
  • Two Low Power General Purpose Rail-to-Rail Analog Comparators (ACMPxL)
  • Two Voltage References (Vref)
    • Two Vref Outputs
  • Eleven Combination Function Macrocells:
    • Three Selectable DFF/Latch or 2-bit LUTs
    • One Selectable Programmable Pattern Generator or 2-bit LUT
    • Six Selectable DFF/Latch or 3-bit LUTs
    • One Selectable Pipe Delay or Ripple Counter or 3-bit LUT
  • Eight Multi-Function Macrocells
    • Seven Selectable DFF/Latch or 3-bit LUTs + 8-bit Delay/Counters
    • One Selectable DFF/Latch or 4-bit LUT + 16-bit Delay/Counter
  • Serial Communications
    • I²C Protocol Interface
  • 2-Kbit (256 x 8) I2C-Compatible (2-Wire) Serial EEPROM emulation with Software Write Protection
  • Programmable Delay with Edge Detector Output
  • Deglitch Filter with Edge Detector
  • Three Oscillators (OSC)
    • 2.048 kHz Oscillator
    • 2.048 MHz Oscillator
    • 25 MHz Oscillator
  • Analog Temperature Sensor
  • Power On Reset (POR)

 

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