Power factor correction shapes the input current drawn from the AC mains so that it closely follows the voltage waveform, improving the ratio of real power to apparent power (power factor). Without PFC, a switched-mode power supply draws non-sinusoidal, peaky current that increases harmonic distortion, stresses the AC distribution system, and reduces the usable power from a given outlet or circuit.

In modern offline PSUs, PFC is implemented as a dedicated AC-DC stage ahead of the DC-DC converter. Totem Pole PFC (TPPFC) is increasingly used because it eliminates the input diode bridge entirely - removing both the diode bridge conduction losses and the PFC diode losses. In a conventional boost PFC, the input diode bridge alone can account for approximately 1.7% of input power loss at low line. TPPFC removes this loss path while achieving near-unity power factor.

Two converging pressures drive this: 

Efficiency: Data center and server PSUs are measured against the 80 PLUS certification tiers. To qualify for 80 PLUS Titanium - the highest tier - a 3.3 kW PSU with 230 VAC input must sustain 96% efficiency at 50% load. Every percentage point of loss translates directly into waste heat that must be managed, increasing cooling cost and reducing reliability. 

Power density: Higher switching frequencies allow smaller magnetics, capacitors, and PCB footprint - enabling either more power in the same physical form factor or the same power in a smaller one. This is critical in rack-mounted server environments governed by standards like the Open Rack specification, where physical space per PSU slot is fixed. 

The trade-off is that higher switching frequencies increase switching losses and thermal stress - making the choice of switching device, controller, and gate driver critical to achieving both targets simultaneously. 

Sources: CJFET Tutorial (80 PLUS Titanium, Open Rack, power density vs. frequency trade-off)

Wide-bandgap (WBG) semiconductors - silicon carbide (SiC) and gallium nitride (GaN) - offer fundamental material advantages over silicon:
 

• Higher breakdown field (~10× Si): Enables higher blocking voltages in smaller die, reducing on-resistance per unit area.
• Higher thermal conductivity (SiC: 3-5× Si): Allows more power dissipation per unit area before thermal limits are reached.
• Higher electron drift velocity (~2× Si): Supports faster switching transitions with lower switching losses.
• Lower or zero reverse recovery: SiC Cascode JFETs exhibit Qrr ≈ 0, eliminating reverse recovery losses during high-frequency commutation. This is particularly impactful in Totem Pole PFC, where the fast leg switches at the PWM frequency and reverse recovery directly reduces efficiency.

In practice, these properties enable PSU designs to operate at higher switching frequencies with lower total losses - improving both efficiency and power density compared to silicon-only designs.

SiC Cascode JFETs are most impactful in the high-frequency switching stages of a multi-stage PSU:
 

• Totem Pole PFC (fast leg): The fast-switching leg operates at the PWM frequency under hard-switching conditions. SiC CJFETs' zero reverse recovery (Qrr ≈ 0) and low switching losses (Eon, Eoff) directly improve PFC stage efficiency. In a 3.6 kW TPPFC test, SiC CJFETs achieved >99% peak efficiency at half load.
• LLC resonant converter (primary side): The LLC primary operates under soft-switching (ZVS) conditions, where low output capacitance (Coss) and fast switching transitions maximize resonant conversion efficiency.
• LLC secondary synchronous rectification: Fast body-diode-free switching reduces rectification losses at the output.
• O-Ring / hot swap: The final stage before the bus bar, where low RDS(on) (down to ~5 mΩ) minimizes conduction losses in continuous-load operation.

A key advantage across all these stages is that SiC CJFETs use a standard 0–12 V gate drive - the same as a silicon MOSFET - so they can be adopted without redesigning the gate drive circuit.

Each stage in a multi-stage PSU operates under different voltage, frequency, and switching conditions - so the optimal device technology differs by position:
 

This is also why each switching position requires a different gate driver - from bootstrap half-bridge drivers on the slow leg to galvanically isolated drivers with ≥200 V/ns CMTI on the fast leg. The campaign's three technology sub-pages (SiC Cascode JFETs, Controllers, Gate Drivers) map onsemi's portfolio to each of these positions.

In a typical two-stage offline PSU:

Stage 1 - PFC (AC-DC): The PFC stage takes the rectified AC input and produces a regulated DC bus (typically ~390-400 VDC). Its primary job is to shape the input current for near-unity power factor while regulating the bus voltage. In high-efficiency designs, Totem Pole PFC replaces the traditional diode bridge + boost PFC, eliminating bridge losses and achieving PFC-stage efficiencies above 99%.

Stage 2 - LLC (DC-DC): The LLC resonant half-bridge converter takes the regulated DC bus and produces an isolated, lower-voltage DC output (e.g., 12 V or 48 V). The LLC topology operates under zero-voltage switching (ZVS) conditions across its load range, meaning there is no turn-on switching loss - the primary-side switches turn on at zero voltage. This enables high-frequency operation with minimal switching losses.

Coordination between stages: The PFC controller regulates the DC bus voltage, while the LLC controller regulates the output voltage. The two stages must be coordinated so that the DC bus remains stable under transient load conditions. In onsemi's portfolio, this is addressed through dedicated PFC controllers (NCP1680 for CrM, NCP1681 for CCM/multi-mode) and current-mode LLC controllers (NCP13994 with integrated 600 V drivers, NCP4390 for secondary-side regulation). Together, these stages form the core of PSU designs from 240 W USB-PD adapters through multi-kW server power supplies.