A SiC Cascode JFET pairs a high-voltage SiC JFET with a low-voltage Si MOSFET in a cascode configuration. The Si MOSFET controls the gate, creating a normally-off device that accepts a standard 0-12 V gate drive - the same as a silicon MOSFET. This eliminates the need for negative gate bias (typically -3 V to -5 V) required by SiC MOSFETs, simplifying gate drive design and reducing component count. SiC CJFETs also exhibit zero reverse recovery (Qrr ≈ 0) and switching losses that decrease at elevated temperatures - both distinct from SiC MOSFET behavior.

In a Totem Pole PFC, the fast-switching leg commutates at the PWM frequency under hard-switching conditions. Any reverse recovery charge in the switching device creates additional losses during each commutation event - losses that scale directly with switching frequency. SiC Cascode JFETs exhibit Qrr ≈ 0, eliminating this loss mechanism entirely. This is the dominant efficiency advantage in TPPFC fast-leg operation and a key enabler for PFC stage efficiencies exceeding 99%.

SiC Cascode JFETs exhibit a distinctive thermal behavior: switching losses (Eon, Eoff) decrease at elevated temperatures, improving efficiency under real-world operating conditions. This contrasts with SiC MOSFETs, where switching losses can increase with temperature. RDS(on) has a positive temperature coefficient, which increases conduction losses slightly at high temperatures but enables natural current sharing when devices are paralleled - a net advantage for high-power PSU designs.

Yes. The positive temperature coefficient of RDS(on) in SiC Cascode JFETs naturally balances current between paralleled devices - a device running hotter sees higher RDS(on), which reduces its current share and prevents thermal runaway. This enables straightforward paralleling for higher-power PSU stages without complex balancing circuits. Detailed guidance on paralleling techniques, layout considerations, and current sharing behavior is covered in the application note "Paralleling SiC Cascode JFETs."

SiC Cascode JFETs use a standard 0-12 V gate drive, making them compatible with conventional MOSFET gate drivers. No negative gate bias is required. In a multi-stage PSU, the gate driver selection depends on the switching position: a bootstrap half-bridge driver (e.g., NCP51530) is sufficient for the PFC slow leg, while the PFC fast leg and LLC primary may require galvanically isolated drivers (e.g., NCP51561) for safety and dv/dt immunity. The Gate Drivers page maps specific onsemi drivers to each PSU switching position.

Both are wide-bandgap technologies, but they address different design trade-offs. SiC Cascode JFETs offer higher voltage ratings (650 V-1200 V), lower RDS(on) at high current (down to ~5 mΩ), and superior thermal conductivity - making them suited for high-power PSU stages (1 kW+) where thermal management and conduction losses dominate. GaN HEMTs excel at very high switching frequencies in lower-power, high-density designs where parasitic inductance must be minimized. For data center intermediate bus converters, the choice depends on bus voltage, power level, and switching frequency - a detailed comparison is provided in the application note covering GaN HEMT, SiC MOSFET, and SiC Cascode JFET for AI datacenter IBC applications.