Enabling safe, efficient switching transitions across PFC and DC-DC power stages
Gate drivers translate low-power control signals into the high-current drive pulses needed to turn power switches on and off. In PSU designs, gate driver performance directly determines switching speed, switching losses, dv/dt immunity, and safe operating margins - constraints that intensify as designs move to WBG switches (SiC, GaN) operating at higher voltages, higher frequencies, and faster slew rates.
Poor gate drive pairing leads to incomplete turn-on, excessive switching losses, parasitic ringing, and accidental turn-on during high dv/dt transitions. At higher power levels, the absence of galvanic isolation between high-voltage and low-voltage domains adds a direct safety risk. Even the gate drive voltage swing matters: switching from a 15 V swing to a 21 V swing (-3 V to +18 V) can reduce Eoff losses by up to 25% per switching cycle on a 1200 V SiC MOSFET - headroom that compounds at every switching transition across the full load range.
onsemi addresses these constraints with a coordinated gate driver portfolio spanning non-isolated bootstrap half-bridge drivers (e.g., NCP51530, FAN7191) for PFC slow-leg and LLC stages; galvanically isolated dual-channel drivers (e.g., NCP51561, NCP51563) with 5 kV isolation and ≥200 V/ns CMTI for PFC fast-leg and LLC primary stages; isolated single-channel drivers with integrated negative bias control (e.g., NCP51752) that eliminate the need for an external negative supply; dedicated GaN half-bridge drivers (e.g., NCP51810) for external GaN HEMT switching stages; and integrated driver-GaN devices (e.g., NCP58921) that combine driver and GaN HEMT in a single package to minimize parasitic inductance.
PSU Architecture and Gate Driver Mapping
In multi-stage PSU architectures, gate drivers are required at each switching position - each with different speed, isolation, and voltage requirements. The PFC slow leg switches at line frequency and needs a bootstrap half-bridge driver. The PFC fast leg switches at the PWM frequency with WBG devices and requires galvanic isolation to handle high dv/dt. The LLC primary half-bridge also requires isolated drive for safe, high-frequency operation. And the LLC secondary SR stage demands the fastest switching speed at lower voltage to maximize rectification efficiency
| PSU Switching Position | Gate Driver Requirements | Example OPNs |
|---|---|---|
| PFC Slow Leg - Line-frequency switching; superjunction MOSFETs | Bootstrap half-bridge driver; moderate speed; 600 V junction isolation sufficient | NCP51530, NCP5183, FAN7191 |
| PFC Fast Leg - PWM-frequency switching; SiC MOSFETs, SiC CJFETs, or GaN | Galvanic isolation (3.75-5 kV); high CMTI (≥200 V/ns); negative bias for SiC; or integrated driver-GaN for minimal parasitic inductance | NCP51561, NCP51752, NCP58921 (iGaN) |
| LLC Primary Half-Bridge - Resonant switching; SiC, GaN, or SJ MOSFETs | Isolated drive with matched propagation delays; dead-time control; or integrated 600 V drivers within the LLC controller (e.g., NCP13994) | NCP51561, NCP58922 (iGaN), NCP13994 (integrated) |
| LLC Secondary SR - High-speed synchronous rectification; LV MOSFETs | Very fast switching; low-voltage junction-isolated half-bridge driver; minimal propagation delay | NCP81705 |
Gate driver selection at each position depends on the switching device technology (Si, SiC, GaN), the required isolation level, and the dv/dt environment. onsemi portfolio scales across PSU power levels - from non-isolated bootstrap drivers in 140 W USB-PD adapters, through galvanically isolated dual-channel drivers and iGaN in 240 W to 1 kW UHD designs, to multi-driver configurations with negative bias control in 3 kW+ server and industrial power supplies.
onsemi Gate Driver Core Properties and Value Drivers
| Core Property | What it Delivers | Example Orderable Part Numbers |
|---|---|---|
| Galvanic Isolation & Safety | 3.75-5 kVrms isolation; supports up to ~1200 VDC working voltage; safe separation between HV and LV domains in high-power PSUs | NCP51561, NCP51563, NCP51752, NCD57090, NCD57100 |
| Integrated Negative Bias Control | As low as -8V gate bias during turn-off; reduces Eoff losses and prevents parasitic turn-on; removes need for external negative supply | NCP51752, NCP57100 |
| High CMTI & dv/dt Immunity | ≥200 V/ns CMTI; maintains signal integrity across isolation barrier during fast switching transitions | NCP51561, NCP51563, NCP51752, NCP51153 |
| Fast & Matched Propagation Delays | ~36 ns propagation delay; ≤5 ns channel matching; enables precise dead-time control and minimizes cross-conduction risk | NCP51561, NCP51563, NCP51752, NCP51152 |
| High Source/Sink Drive Current | Up to 4.5 A / 9 A (standard) or 7 A / 7 A (advanced); ensures fast gate charge/discharge at high switching speeds | NCP51561, NCP51752, NCD57090, NCD57100 |
| Integrated Driver-GaN (iGaN) | Driver + GaN HEMT in one package; minimizes parasitic inductance; enables clean high-speed switching (>100 V/ns) | NCP58920, NCP58921 |
| Active Protection Suite | Active Miller clamp, DESAT, UVLO options; protects against dv/dt-induced turn-on and short-circuit events | NCD57080, NCD57090, NCD57100, NCP51152 |
| Bootstrap & Non-Isolated Half-Bridge | Cost-effective high-side drive; suited for line-frequency stages and applications where isolation is not required | NCP51530, FAN7191 |
These properties span onsemi's PSU gate driver portfolio - from bootstrap drivers in 140 W+ adapters to isolated SiC-optimized drivers with integrated negative bias in multi-kW server PSUs, and iGaN devices enabling >36 W/in³ power density.
Role of onsemi Gate Drivers in Power Stage
| Functional Role (Driver Level) |
Operating Conditions (Power Stage Context) |
System Impact (Outcome) |
|---|---|---|
| Bootstrap half-bridge drive for PFC slow leg (e.g., NCP51530, NCP5183, FAN7191) | Line-frequency switching (50/60 Hz); SJ MOSFETs; moderate dv/dt | Cost-effective drive for low-speed switching; no galvanic isolation overhead |
| Galvanically isolated drive for PFC fast leg (e.g., NCP51561, NCP51752) | PWM-frequency switching with WBG devices (SiC, GaN); high dv/dt (≥200 V/ns); requires safety isolation | Safe, high-speed switching with full gate charge delivery; negative bias prevents parasitic turn-on during fast transitions |
| Integrated driver-GaN for PFC fast leg and LLC (e.g., NCP58921, NCP58922) | High-frequency switching (up to 500 kHz); dv/dt >100 V/ns; parasitic inductance must be minimized | Driver + GaN in single package eliminates lead and PCB trace inductance - enables clean switching and higher power density |
| Isolated half-bridge drive for LLC primary (e.g., NCP51561, NCP51563) | Resonant half-bridge stage; matched timing critical for ZVS; dead-time control required | ≤5 ns propagation delay matching ensures symmetric half-bridge operation; programmable dead-time prevents cross-conduction |
| Integrated 600 V drive within LLC controller (e.g., NCP13994) | LLC primary stage where external driver is not required; simplifies layout | Eliminates external driver and level shifter - reduces component count and PCB complexity |
| High-speed junction-isolated drive for LLC secondary SR (e.g., NCP81705) | Very high switching frequency; low-voltage MOSFETs; fastest propagation delay needed | Maximizes SR conduction time and minimizes body-diode losses at the output stage |
| Negative bias control for SiC MOSFET turn-off (e.g., NCP51752, NCP51753) | SiC switching stages where −3 V to −5 V gate bias is needed to prevent accidental turn-on during high dv/dt | Saves ~100 µJ Eoff per cycle; provides 3–5 V headroom against VGS threshold trip; eliminates external negative supply |
| Active protection - Miller Clamp, DESAT, UVLO (e.g., NCD57080, NCD57100) | Fault and abnormal conditions across PFC and LLC stages; short-circuit events | Prevents parasitic turn-on (Miller Clamp); detects short-circuit with soft turn-off (DESAT); matched UVLO thresholds for Si/IGBT/SiC |
Technical resources to support your system design and evaluation
Tutorials & Application Notes
- Pairing Gate Drive to EliteSic Tutorial
- Practical Design Guidelines on the Usage of an Isolated Gate Driver
- Design and Application Guide of Bootstrap Circuit for High-Voltage Gate-Drive IC
White Papers
- 3 kW Totem−Pole PFC and Secondary−Side Regulated LLC Power Supply Using SiC MOSFETs
- Totem Pole PFC Layout Considerations
- Meeting Ultra−High−Density Design Challenges with GaN−based 300 W Totem Pole PFC and LLC Power Supply
- Enhancing Performance, Efficiency and Safety with SiC Isolated Gate Drivers
- SiC MOSFETs: Gate Drive Optimization
Reference Designs & System Solution Guides
Frequently Asked Questions (FAQs)
Galvanic isolation is required when gate drivers interface between low-voltage control circuits and high-voltage switching nodes. It prevents ground potential differences from propagating into the control domain and protects against high-voltage transients. Isolation becomes critical in PFC fast-leg and LLC primary stages, where high dv/dt and voltage levels are present.
Negative gate bias (typically -2 V to -5 V) improves turn-off behavior by suppressing unintended turn-on and reducing switching losses. In practice, applying negative bias can reduce Eoff losses by up to ~25%, depending on the device and operating conditions, while improving robustness during high dv/dt transitions.
Runt pulses are typically caused by mismatched propagation delays or insufficient drive timing control. Using gate drivers with fast and tightly matched propagation delays (e.g., ≤5 ns mismatch) allows accurate dead-time control and prevents incomplete switching events, especially in half-bridge configurations operating at high frequency.
High-speed SiC and GaN switching stages require high common-mode transient immunity (CMTI) to maintain reliable signal transmission across isolation barriers. In practice, gate drivers with ≥200 V/ns CMTI are typically required to ensure stable operation during fast switching transitions and high dv/dt conditions.
Different switching positions in a PSU impose distinct voltage, speed, and isolation requirements. The 3 kW reference design uses multiple gate drivers because:
- PFC slow leg → line-frequency switching (non-isolated)
- PFC fast leg → high-frequency WBG switching (isolated)
- LLC primary → high-frequency half-bridge (isolated)
- LLC SR → low-voltage, high-speed switching
Each stage requires a gate driver optimized for its specific switching conditions.
Use integrated driver-GaN (iGaN) when:
- Minimizing parasitic inductance is critical
- High switching frequency and power density are priorities
- Compact layout and simplified design are required
Discrete gate driver + FET solutions remain suitable where design flexibility or device selection control is needed. Integrated iGaN devices enable faster switching, lower losses, and smaller form factors.
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