From trace to interconnect: a quick guide to optimising high-speed signal-path design

By Martin Keenan   |   November 23, 2020

Designers of almost any type of equipment, from IoT gateways and edge devices to data-centre servers and network-infrastructure cards, are under pressure to move more data, more quickly into, through and out of their systems.

Today’s affordable high-speed ICs let designers easily scale system speeds to meet end-user demands. On paper. On the board, and throughout the system’s interconnections, effects such as common-mode noise, crosstalk, and losses due to signal-path impedances and resonances can challenge the integrity of signals at Gbit/s speeds and above.

The causes of these unwanted effects include coupling, external noise sources, and the physical characteristics of interconnections. Although these are usually negligible at lower speeds, more care must be taken when designing and arranging the signal paths to handle high-speed signals.

Growing adoption of high-speed encoding schemes promises to sustain the upward trend of multi-Gigabit data rates. As familiar two-level NRZ (non-return-to-zero) signalling comes up against physical limitations at data rates much above 28Gbps, four-level PAM4 signalling handles 56Gbps and higher, and is a key enabler for future 200G and 400G Ethernet speeds.
 

Interconnect design for signal integrity

Differential signalling is widely used in high-speed systems to cancel the effects of external noise coupled onto signal lines. The layout of the signal-path pairs, including path lengths and spacing, can have a critical impact on signal integrity. The paths should be as short as possible and trace length matching is usually required, although not with standards such as PCIe that contain an embedded clock signal. Design guides for high-speed interconnects such as USB3.0, HDMI, and others typically provide information such as the maximum recommended trace lengths, spacing between signal pairs and other signal traces, and the spacing to clock signals.

The 5S, or 5W, rule of thumb is commonly applied to calculate the appropriate pair-to-pair spacing, and calls for the spacing to be at least five times the trace width. While intra-signal pairs are usually closely spaced, it is important to ensure consistent spacing along the full length of the trace to prevent changes in differential impedance that can impair signal integrity. Consistent spacing also helps to maintain the magnetic-field cancelling effect of the differential pair, which minimises electromagnetic emissions (radiated EMI).

Interconnect design guidelines also provide valuable information about board stackup. Confining the high-speed signal traces to the upper layer avoids the use of vias that introduce extra inductance into the signal path. HDMI guidelines recommend a separation of 125-250 microns between the upper signal plane and the adjacent ground plane. Non high-speed signals should be routed on lower layers to maximise separation from the high-speed signals. This calls for at least a four-layer stackup.

Routing the traces over solid ground plane metal is also recommended, routing around features such as voids or plane splits. A gap of at least 1.5x the trace width can prevent the high-frequency signal current interacting with the discontinuity in the ground plane, which can otherwise cause signal disturbances, increased EMI, and propagation delays. High-speed routing should also avoid components such as crystals, oscillators, and switching power regulators, and board designers should also avoid placing probe or test points on high-speed traces.
 

Connector selection and mounting

When it comes to introducing components and connectors in high-speed signal paths, surface-mounting is usually preferred. When the high-speed signals are routed on the upper layer, the connection can be made directly without requiring vias. If a via is needed, to connect from a lower layer, back-drilling may be required to prevent the unused metal acting as a stub in the signal path, which can cause significant signal degradation.

If high-speed signals are to be taken off the board, to an adjacent board or through a cable to another part of the system, those components become part of the signal path and must be considered as carefully as the board design. Inappropriate connector selection, or a poorly designed cable assembly, can allow mismatches, resonances, and interference to creep back into the system.

Connectors designed for high-speed applications contain features conceived to help maintain signal integrity. One example is the Molex Mirror Mezz series of high-density stackable board connectors for data speeds up to 56Gbps. Featuring a cost-effective ball-grid array (BGA) for surface-mount attachment, these connectors provide a Ground-Signal-Signal-Ground (GSSG) pin arrangement that is ideally suited to differential signalling.

The GSSG sequence is commonly used to preserve high-speed signal integrity. The ground connections are so arranged to shield differential pairs from other transmission lines. In Mirror Mezz connectors, the ground pins have been made especially wide to provide enhanced shielding and help to balance electrical fields. Open pin-field rows available on some variants, in offset GSSG pinout, provide nine signal pins on an 8.10mm pitch and support differential signals up to 17GHz. The signal pins are electrically tuned for high signal integrity and shaped to minimise crosstalk between adjacent rows.

At the same time, the mechanical design is conceived to ensure reliable electrical continuity. The terminals are designed to eliminate terminal lift and vibration. Two points of contact when mated, with careful management of forces and wipe area, maintain engagement when subjected to high vibration or if the connector is partially unmated. Mirror Mezz also offers dedicated flex cable links that feature controlled channels and pinned grounds to preserve signal integrity when connecting boards in flexible architectures.

It’s also worth noting that the high density of the Mirror Mezz connectors allows designers to connect a large number of signal pairs within a relatively small board area thereby permitting a large total interconnect bandwidth.
 

Connector and cable systems

Cable interconnects can also be vulnerable to signal degradation. A system solution, such as the Molex iPass Interconnect System comprises connectors and cable assemblies for internal and external applications. Designed for applications up to 14Gbps, the host connector is a surface-mount design that can be placed on either side of the PCB, allowing the engineer to make best use of the board. The cables are designed to provide tight skew control and low crosstalk. The system is well suited to server-storage applications, with standard external cables for Serial Attach SCSI (SAS), Serial ATA (SATA), Serial Rapid I/O (SRIO), and Ethernet, with features that minimise external plug width and assist with cable management.

The Nano-Pitch I/O connector system is smaller still, and ideal for mobile applications as well as storage systems, host bus adapter (HBA) servers, and network switches and routers. With staggered dual-row contacts, the receptacles provide optimal routing for high-speed trace connections within a compact footprint. The GSSG pinout is designed to maximise the number of high-speed lanes, including four-lane and eight-lane industry-standard sizes, within a small form factor. Suitable for applications up to 25Gbps, the system is compatible with all the PCIe, SAS, and SATA protocols and is ready for PCIe Gen 4 and SAS 4.

Conclusion

Designers of high-speed system hardware must employ best practices to ensure proper signal integrity at Gbps speeds and above. Starting at the beginning with the PCB layout, the entire signal path needs to be designed carefully, including selecting appropriate connectors and cables for the signal speeds that are expected to be encountered. If you're designing high-speed signal paths, register for our webinar 'Optimising signal integrity in high speed industrial, automotive and healthcare applications' to take a deep dive with Molex's Zach Bradford. Alternatively, if you would like to discuss your design with one of our technical specialists, click the Ask an Expert button to get in touch.

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Martin Keenan

As Technical Director, Martin is responsible for technical marketing strategy across IP&E, power and...

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