Addressing the processing needs of Space 2.0 applications

By Paul Leys   |   August 9, 2023   |   Provided By Avnet Silica

The heavens may be infinite, but in Earth’s neighbourhood things are getting crowded. Space 2.0, a new era of exploration and development driven more by commercial interests than government action, is fuelling rapid innovation in reusable rockets, satellite internet connectivity, Earth observation platforms, navigation, space tourism and many more applications. As a result, our skies are rapidly becoming much busier than ever before.

For instance, internet connectivity services are proliferating. Elon Musk’s Starlink offering has already launched more than 3,580 satellites into low-earth orbit (LEO). Meanwhile OneWeb, another market contender, used its 18th rocket launch, in March 2023, to deploy 36 satellites to complete its 618-strong constellation. And Amazon’s Project Kuiper plans to use up to 92 rocket launches over the next few years to deploy a constellation of 3,236 satellites. 

There’s plenty of activity in other sectors as well, such as earth observation, to help track climate change; navigation for terrestrial and off-world vehicles; avionics, defence, and security applications; and even for hobbyists. Many of these applications require significant computing power to handle dense data streams, such as large numbers of detailed images, and more powerful communications to provide links between satellites in orbit and to the ground. They need more advanced hardware acceleration to handle specialised tasks with greater energy efficiency. Additionally, they need machine-learning (ML) capabilities to enable greater autonomy, for example, in handling path estimation and collision avoidance in increasingly crowded orbits.

The Space 2.0 era also signifies that the industry is facing commercial pressures like never before, with a shift from bespoke to mass production of satellites and launchers, downward pressure on costs, reduced time to market, as well as demands for greater functional integration and more on-orbit flexibility to enable satellites and spacecraft to adapt in orbit. Manufacturers also need to build electronics that can operate in the harsh environment of space, utilising specialised device-packaging technologies qualified to very high standards to resist the effects of radiation, extreme thermal cycling, and the mechanical stress of launch, among others. Moreover, manufacturers must also commit to provide long-term support and supply guarantees for their space grade parts.

Adaptive compute acceleration platforms to the rescue

One well-established approach to addressing such complex challenges is the use of programmable logic, which began as a flexible way to implement glue logic and has gradually absorbed dedicated processor, signal-processing, memory, and I/O functions to become the basis for true systems on chip (SoCs). Xilinx has been at the forefront of this evolution, and since its acquisition by AMD in 2022, it has also had access to the processor company’s expertise in silicon process development as well as their own, 2.5 and 3D functional integration and packaging strategies and insights on ML architectures.

Out of this combination of experience, technology and market insight has come AMD XQR VERSAL™ adaptive compute acceleration platforms (ACAPs), a family of adaptable SoCs for space applications. They are built on a 7nm process that has been tuned to reduce the effect of single event upsets (SEUs) caused by radiation, and variants within the family can host different mixes of CPUs, DSP and ML accelerators, programmable logic, and memory resources, as well as advanced peripherals and I/O facilities. Importantly, the ability to configure the parts is not affected by exposure to radiation, enabling a payload’s processing functions to be regularly updated when in use in space.

Three key aspects of the XQR VERSAL architecture

The XQR VERSAL components boast robust processor, AI Engines, and on-chip networking facilities, in addition to many other supporting functions that programmable SoCs have accumulated over the years.

The XQR VERSAL’s processor system has an application processor based on a 64bit dual-core Arm® Cortex®-A72, and a real-time processor based on a 32bit dual-core Arm Cortex-R5F design. The scalar engines run complex algorithms and decision making for autonomous systems, providing safety processing and redundancy for mission- and safety-critical applications. Peripherals are used to connect to external devices over industry-standard protocols, including USB, Ethernet, I2C, and others. 

A platform management controller is an essential component that helps manage the overall device and its power consumption. It operates within its own power domain and handles power management and reset for all functional blocks, handles errors, deals with configuration, and provides analogue measurements. Additionally, the controller features two triple-redundant MicroBlaze processor blocks, along with peripherals that become available to the main processors once the system is booted. The MicroBlaze processors can be used to run ‘scrubbing’ algorithms, which can detect and correct SEUs caused by radiation in the configuration SRAM cells, without having to reset the whole device.

Each XQR VERSAL part also has a cluster of AI Engines to handle ML and artificial intelligence (AI) workloads. This is made up of a two-dimensional array of ‘adaptive intelligent engines’, each of which has a 32bit scalar RISC core, 512bit SIMD vector processor units (both fixed- and floating-point), 16Kbyte of local memory, and two 256bit load and store units supported by individual address generation units. This architecture helps ensure that the overall AI Engine can support multiple levels of parallelism, at both the instruction and data levels. The overall AI Engine Clusterhas been designed to accelerate a balanced set of workloads, including ML inference applications, and advanced signal-processing functions such as beamforming, radar, FFTs, and filters.

The third key aspect of the XQR VERSAL architecture is its Network on Chip (NoC), which provides an aggregate of about 400Gbit/s of on-chip bandwidth between its major functional blocks, as well as providing access to off-chip data through DDR memory controllers and Gigabit transceivers. The NoC is built directly in the silicon, rather than being instantiated through the programmable logic fabric, which saves logic resources and avoids the timing and power-consumption issues this approach can cause. The NoC has vertical and horizontal routing resources, implements packet switching to buffer and arbitrate data-movement conflicts, and can also implement some streaming data protocols.

Space qualifications

Electronic components that are going to operate in space need to be adapted to the harsh environment, offering very high production quality and reliability (because they are not repairable in service), as well as strong resistance to the effects of radiation, which can flip the values of memory bits or damage circuitry. 

AMD screens its space-grade parts to meet the requirements of the US Department of Defense’s MIL-PRF-38535 Class B manufacturing quality standard, adapted by the company to take into account the characteristics of organic packages that are different to those of the ceramic packages that the MIL-PRF-38535 specification was originally created for. The military standard includes requirements for stringent tests such as high temperature operating life and temperature cycling, but AMD uses even more rigorous qualification testing. Qualification for the XQR VERSAL parts is already well underway, and interested customers can request a complete timeline for this from the company.

AMD has also made considerable progress in characterising the performance of the XQR VERSAL parts when subjected to radiation. This has been carried out under both proton bombardment, as this is present in low-earth orbit, and with the heavy ions found at higher, geosynchronous orbits. Total dose testing was carried out under gamma radiation.

The key result of testing is to show that there have been no single event latch-up events, in which a low-impedance path between power and ground is created, even under high-energy heavy ion bombardment at 125 degrees C. AMD  has also tested the configuration memory (C RAM), and has found that the native uncorrected upset rate of the CRAM is about 3.5 x 10^–9 upsets per bit day in LEO, and much less in geosynchronous orbit. However, all CRAM upsets detected in testing were correctable, which means that the scrubbing software that runs on the platform management controller can correct all CRAM upsets without resetting the device. 

AMD has also tested the XQR VERSAL’s processing system and has found that the aggregate single-event functional interrupt performance for all the real-time processors, the platform management controller, and the NOC, is just over one event per year in LEO, and once every six years in GEO.

Power estimation

For power estimation, AMD has introduced a Power Design Manager, a Java® based estimation tool that simplifies manual power estimation and can import XPE files generated by the Vivado tool. Considering the harsh thermal environment of space and the significant power flowing through the XQR VERSAL parts, AMD recommends using computational fluid dynamics tools to simulate localised thermal dissipation and heat flows within a space system design.

Conclusion

Space may be infinite, but Earth’s neighbourhood is becoming much busier as the Space 2.0 era rapidly increases the number of satellites and spacecraft in orbit. This is creating demand for ‘adaptive compute acceleration platforms’, that is, powerful, flexible, and reconfigurable hardware that can handle generalist tasks quickly and which also bear dedicated resources for handling specialist tasks such as signal processing and machine inference.  AMD XQR VERSAL parts, enhanced by access to AMD’s process and packaging expertise and with strong protections against radiation-induced errors, are ideal building blocks for fast-moving Space 2.0 applications.

Renesas Solutions

With ever more complex processing solutions needed for space, there is a growing requirement for reliable, robust and lower-cost power supply solutions. The ISLVERSALDEMO2Z demo board provides the power management for the AMD Space Grade Versal ACAP AI Core VC1902 using Renesas' Radiation Hardened Power Management devices. 

The Versal ACAP system requires various supply rails, including the core, digital, analog, and DDR memory. The ISLVERSALDEMO2Z provides all these rails for the user to evaluate the performance against the Versal ACAP DC and AC electrical specifications.

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Paul Leys

Paul Leys is the Market Segment Manager for the Aerospace and Commercial Avionics business at Avnet ...

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