Versal Adaptive SoC Architecture and Design Flow
30 Nov 2026 - 30 Nov 2026
Germany, Hamburg
Join Avnet Silica and AMD for a technical workshop dedicated to the latest innovations in Adaptive SoC design. This event will explore how AI-assisted development is transforming engineering workflows and provide practical insights into high-speed connectivity and RF design challenges.
Through live demonstrations, expert presentations, and real-world design examples, attendees will discover new methodologies, tools, and best practices to accelerate development, improve productivity, and optimize system performance using the latest AMD technologies.
Whether you are an FPGA designer, embedded software engineer, system architect, or hardware developer, this workshop will equip you with valuable knowledge that can be applied directly to your next project.
Datum & Ort
- 9:00 - 17:00, November 30th, 2026 - Deutsches Elektronen-Synchrotron DESY, Notkestraße 85, 22607 Hamburg, Germany
Agenda
Session 1: Agentic AI for Adaptive SoC Development
Discover how AI-powered agents can accelerate and simplify Adaptive SoC development through practical demonstrations and real-world examples.
- Accessing relevant AMD documentation and technical knowledge
- Driving Vivado™ and Vitis™ HLS
- Supporting hardware interaction and system validation
- Automating complex engineering workflows
- Integrating AI agents into engineering teams
Session 2: High-Speed GTs, RFSoC & Versal RFt
A technical deep dive into designing, configuring, optimising, and debugging high-speed and RF solutions.
- GT architectures and design considerations
- GT equalizer configuration, tuning and debugging
- Performance optimisation using IBERT
- RFSoC and Versal RF platforms
- ADC/DAC architecture and signal-chain optimisation
- Frequency Planner for efficient system design
Partners
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