AMD Embedded Tour 2026
09 Jun 2026 - 09 Jun 2026
Milan, Italy
Join Avnet Silica for the AMD Embedded Tour – Milan
The AMD Embedded Tour is back for 2026 and returns once again to Milan, bringing a full day of practical, engineering focused insight to one of our most established locations. Built around real design challenges, this one day event helps engineering teams manage system complexity and make confident technology decisions for their next generation of products.
This year’s Milan programme features a deep technical agenda shaped around the needs of local engineering teams. Topics range from design optimisation on AMD Versal™ and Spartan™ UltraScale+™ devices, to system level best practices for adaptive hardware development. The day also explores key technology areas including the AMD Programmable NoC, boot and configuration flows, MicroBlaze™ V processor and Zephyr, frequency planning for RFSoC/Versal™ RF, and essential cybersecurity considerations for FPGA/SoC designs.
Engineers will also gain high value updates across the wider AMD portfolio, covering the current AI/ML landscape with AMD Vitis™ AI, industrial robotics and healthcare applications, aerospace and high-reliability developments (FPGA + x86).
Whether you’ve attended previous editions in Milan or are joining us for the first time, the AMD Embedded Tour 2026 is designed to help you accelerate problem solving, reduce design risk, and build systems ready for the future.
Date & Location
9 June 2026 - UNA Hotels Expo Fiera Milano, Via Giovanni Keplero, 12, 20016 Pero MI, Italy
Agenda
| Time | Session | |
|---|---|---|
| 08:30 | Registration | |
| 09:00 - 09:15 | Welcome and Opening Remarks Setting the scene for the day, outlining key themes and what attendees can expect from the programme. |
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| 09:15 - 10:00 | AMD Adaptive SoC Portfolio and Applications, Including x86 Embedded A detailed overview of the latest AMD Adaptive SoC families, highlighting new capabilities and real world applications, including innovations powered by x86 embedded technology. |
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| 10:00 - 10:30 | Coffee break and marketplace | |
| Track 1 | Track 2 | |
| 10:30 - 11:20 | Streamlining Embedded Linux® Development with Yocto Project® Based Frameworks An introduction to Yocto Project® based embedded development frameworks for building and deploying code on hard processing subsystems in adaptive devices. Learn the development flows used to build and deploy Linux® and embedded applications on development kits, enabling a more streamlined embedded software workflow. |
An Introduction to AMD Versal™ Boot & Configuration Modern adaptive SoCs use a different boot and configuration methodology compared to previous generations. This session highlights the Platform Device Image (PDI) boot flow and introduces segmented configuration approaches that enable the processing system to boot independently before the programmable logic, offering greater flexibility in system initialisation. |
| 11:20 - 12:10 | Working with Multi-Giga Sampling ADC/DACs: Frequency Planning and Associated tools This session will quicky go through the AMD ADC/DAC structures before analysing the concepts associated with Direct Sampling: Spectrum folding, Multiple Nyquist Windows management, anti-alias filtering and Frequency Planning. We will then show the features of the AMD Frequency Planner for optimal ADC/DACs setup. |
Introduction to Current AMD AI/ML Landscape, Including New Vitis AI + Demo Deep dive into the current AMD AI/ML landscape, highlighting the latest advancements across hardware, software, and development tools, including an overview of the new Vitis AI features that streamline model deployment and optimisation on AMD platforms. A live demo will showcase practical workflows and real-world performance, helping developers accelerate AI innovation on AMD technologies. |
| 12:10 - 13:00 | Partner Solutions Molex will highlight FPGA, RFSoC and x86 embedded acceleration platforms for high performance embedded and edge computing, while MPS will present its one stop shop power management solutions for AMD FPGA, SoC and CPU platforms. SiTime will showcase MEMS based timing solutions enabling high performance FPGA systems across AI, data centre and industrial applications. |
Cyber Security Aspects on FPGA/SoCs + Demo An exploration of key cybersecurity considerations for FPGA and SoC platforms, highlighting threats, mitigation strategies, and best practices for securing programmable architectures. It includes a live demonstration showcasing practical security features and real world attack prevention techniques, providing designers with actionable insights to strengthen system resilience. |
| 13:00 - 14:00 | Lunch and networking | |
| 14:00 - 14:50 | Industrial Robotics and Healthcare Solutions An overview of the AMD Industrial, Robotic and Health (IRH) solutions, along with the latest updates for aerospace and high-reliability applications using FPGA and x86 technologies. It highlights key platform capabilities, reliability features, and emerging use cases, offering insights into how AMD’s portfolio supports next generation industrial and high-reliability system designs. |
Space Solution Update An update on AMD latest space grade solutions, highlighting advancements in radiation tolerant FPGA and processor technologies. It covers new platform capabilities, reliability enhancements, and key use cases in satellite, deep space, and high altitude applications. Attendees will gain insights into how AMD’s evolving portfolio supports next generation spacecraft architectures. |
| 14:50 - 15:40 | System Design: Best Practices for Adaptive Hardware Development (Deep Dive) Learn best practices for your next adaptive embedded hardware design. Topics include power estimation and analysis, power delivery and decoupling design, thermal design and simulation, power and signal integrity simulation (covering LPDDR5X and 112 Gb/s), and essential schematic and board checklist reviews. Additional labs and training recommendations are provided for continued learning. |
Introduction to Cost Optimised Portfolio, MicroBlaze V and Zephyr The AMD Cost Optimised Portfolio (AMD Spartan™, Artix™, Zynq™) integrates with the AMD MicroBlaze V RISC soft processor and Zephyr RTOS to deliver highly configurable, scalable, open source embedded solutions. Ideal for cost sensitive applications such as environmental monitoring and data acquisition, the portfolio leverages Zephyr and Linux OS support to accelerate innovation and reduce time to market. |
| 15:40 - 16:10 | Coffee break and marketplace | |
| 16:10 - 17:00 | Optimising AMD Versal™ and Spartan™ UltraScale+™ Designs with Vivado™ Design Suite Explore the latest AMD Vivado™ Design Suite features that help with QoR, ease of use, and fast development. Additionally, we describe the new Advanced Flow for AMD Versal™ devices and some optimisations made for increased design performance with AMD Spartan™ UltraScale+™ FPGAs. |
Optimising System Bandwidth with the AMD Versal™ Programmable NoC and NoC Compiler Discover how Network on Chip (NoC) architectures, combined with compiler driven optimisation, can significantly improve system performance. Learn how automated optimisation reduces system resources, improves bandwidth, and enhances scalability in complex adaptive SoC designs. |
| 16:40 - 17:00 | Raffle and Closing Remarks Key takeaways from the day, final remarks, and the closing raffle. |
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Registration