AMD Tech Day Germany
16 Jun 2026 - 24 Jun 2026
Germany, multiple locations
Migrating to SUP and Running Zephyr on MicroBlaze™ V for AMD FPGA Families
Join us for a full-day technical deep dive focused on moving to the Scalable Unified Platform (SUP) and running Zephyr on MicroBlaze™ V (RISC V) across AMD FPGA families.
This Tech Day is aimed at engineers already working with AMD devices who want a clear, practical understanding of SUP migration, updated Kintex™ UltraScale+™ Gen2 availability, and hands-on experience bringing up MicroBlaze™ V with Zephyr, from Vivado to a running application. Working directly with AMD experts, the day combines architecture updates, migration guidance, RTOS fundamentals, and a live, instructor led demo on the SCU35 platform.
Key topics include:
- What changes with SUP and what to consider when migrating existing designs
- Kintex™ UltraScale+™ Gen2 and SUP overview, with a focus on I/O and memory
- RISC V on AMD FPGAs: MicroBlaze™ V positioning and use cases
- Running Zephyr RTOS on MicroBlaze™ V
- Hands-on demo: from Vivado to “Hello Blinky” on SCU35 using MicroBlaze™ V and Zephyr
Dates & locations
- 16 June 2026, Stuttgart, Germany
- 24 June 2026, Hamburg, Germany
Agenda
| Time | Session |
|---|---|
| 09:00 - 10:00 | Open Technical Exchange Meet with our experts - An open, informal session to discuss your current designs, challenges, or roadmap questions with AMD and Avnet Silica experts before the formal agenda begins. |
| 10:00 - 10:15 | AMD Portfolio & Platform Update A concise update on AMD FPGA roadmap, platform direction, and key topics relevant to current and next generation designs. |
| 10:15 - 11:00 | Kintex™ UltraScale+™ Gen2 & SUP Architecture Overview An overview of Kintex™ UltraScale+™ Gen2 devices and the Scalable Unified Platform (SUP), with a focus on I/O capabilities, memory architecture, and updated device availability. |
| 11:00 - 11:15 | Coffee Break |
| 11:15 - 12:15 | Migrating to SUP: Key Differences and Design Considerations A deep dive into what changes when moving to SUP, including architectural differences, tool flow impacts, and practical points to consider when migrating existing designs. |
| 12:15 - 13:15 | Lunch |
| 13:15 - 14:15 | RISC V on AMD FPGAs: Introducing MicroBlaze™ V An introduction to MicroBlaze™ V, AMD’s RISC V–based soft processor, covering positioning, capabilities, and typical use cases compared to traditional MicroBlaze implementations. |
| 14:15 - 15:15 | Zephyr RTOS Fundamentals on MicroBlaze™ V An overview of the Zephyr real time operating system and what it enables on MicroBlaze™ V, including software architecture, ecosystem support, and integration considerations. |
| 15:15 - 15:30 | Coffee break |
| 15:30 - 16:30 | Live Demo: From Vivado to “Hello Blinky” on SCU35 An instructor led, end to end demonstration showing how to bring up MicroBlaze™ V with Zephyr on the SCU35 platform, from hardware design in Vivado to a running application. |
| 16:30 - 17:00 | Technical Q&A Open Q&A to address platform specifics, migration challenges, tool flows, and software questions raised throughout the day. |
| 17:00 | Open Forum An open discussion session for deeper technical conversations, follow up questions, and peer to peer exchange. |
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