Multi-Tile Synchronization Characterization and Performance on the Zynq UltraScale+ RFSoC Gen 3
online, on-demand

Synchronizing data converters is critical for phased array and massive-MIMO applications, and effects like architecture, alignment, temperature, voltage and process can impact performance. In this webinar, we will review the Xilinx Zynq ® UltraScale+ ™ RFSoC data converter structure and recent multi-tile synchronization characterization and performance. A design methodology using HDL Coder ™ from MathWorks will be shown for custom implementations of multi-tile synchronization on the Xilinx ZCU208 evaluation kit.
Speakers
- David Brubaker - Product Line Manager, Zynq Ultrascale+ RFSOC, Xilinx
- Fred Kellerman - Wireless Communications FPGA Sysem Architect, Avnet
RELATED EVENTS

Deploy Edge AI at GPU-level performance
Join Avnet Silica and DEEPX for an exclusive one-hour webinar introducing cutting-edge AI inference acceleration technology now available in Europe.

Avnet Silica Embedded Technology Workshop: Modular Computing, Memory & AMD x86 Embedded Platforms
A compact update on modular embedded solutions, current memory market trends, and the latest developments in the TRIA portfolio and AMD-based x86 board solutions.

AMD Tech Day Rome - AIE for DSP
Avnet Silica, in collaborazione con gli specialisti AMD, è lieta di invitarti al Tech Day dedicato agli AI Engines, la tecnologia alla base delle più avanzate applicazioni DSP sulle piattaforme Versal Adaptive SoC.