Multi-Tile Synchronization Characterization and Performance on the Zynq UltraScale+ RFSoC Gen 3
online, on-demand

Synchronizing data converters is critical for phased array and massive-MIMO applications, and effects like architecture, alignment, temperature, voltage and process can impact performance. In this webinar, we will review the Xilinx Zynq ® UltraScale+ ™ RFSoC data converter structure and recent multi-tile synchronization characterization and performance. A design methodology using HDL Coder ™ from MathWorks will be shown for custom implementations of multi-tile synchronization on the Xilinx ZCU208 evaluation kit.
Speakers
- David Brubaker - Product Line Manager, Zynq Ultrascale+ RFSOC, Xilinx
- Fred Kellerman - Wireless Communications FPGA Sysem Architect, Avnet
RELATED EVENTS

NXP Cyber Resilience Act (CRA) Italy
Il nuovo Regolamento Europeo sulla cybersicurezza, noto come CRA (Cyber Resilience Act), è ora in vigore, con sanzioni applicabili a partire da dicembre 2027 in caso di non conformità.

Deploy Edge AI at GPU-level performance
Join Avnet Silica and DEEPX for an exclusive one-hour webinar introducing cutting-edge AI inference acceleration technology now available in Europe.

AMD Tech Day Germany
This full-day technical seminar gives engineers a practical overview of modern AMD FPGA platforms, with a focus on Kintex™ UltraScale+™ Gen2 and Spartan™ UltraScale+™.