Versal Adaptive SoC Architecture and Design Flow

01 Dec 2025 - 01 Dec 2025

Germany, Hamburg

The flexibility and connectivity of traditional FPGAs has further expanded since the advent of AMD Versal™ Adaptive SoC Family. Evolving from the hardened CPU clusters in Zynq Ultrascale+ MPSoC these devices also allow for custom specific compute acceleration in the FPGA part. To accommodate even higher compute loads the feature set added native vector processing with the Versal™ AI Engines in various subfamilies. Versal devices combine these compute domains with a high bandwidth Network on a chip (NoC) to allow for efficient data path connection between these compute domains.

We will walk through the Versal architecture to foster insight into these features, informing the device nuances and giving insight into the design steps. These involve new design entry, e.g., for the NoC on top of established concepts, which still allow for traditional embedded software development but also support software define acceleration kernel generation. To deploy this approach, we will visit the extensible platform concepts and show how these help with system level integration across the heterogeneous domains of the devices.

Datum & Ort

• 09:00 – 17:00, December 1st, 2025 - Deutsches Elektronen-Synchrotron DESY, Notkestraße 85, 22607 Hamburg, Germany

Agenda

Session 1:

• Versal Adaptive SoC Technology Overview
  • Architecture
  • Design Tool Flow (Hardware)
  • Programmable Logic
  • NoC

Session 2:

• Development with Versal specific IP
  • Memory
  • Processing System and Embedded Design Flow Overview
  • Boot and Configuration
• Extensible Embedded Platform Concepts
  • Hardware, IP and Platform Development

Session 3:

• Brief recap of Versal Architecture
  • Device Family on Block Level
  • Vivado and Vitis Flow for Versal
• Embedded System Software Support
  • Versal Software Stack 
  • SMP and AMP: Multicore software architecture and heterogenous designs

Session 4:

• AI Engines
  • Architecture Overview
  • AI Engine Programming: Kernels and Graphs
• System Integration Approaches
  • System Design Flow
• Versal System Level Design Support
  • Outlook: Vitis Libraries

Registration

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