onsemi EliteSiC JFETs — Built for the Unforgiving

SiC JFETs achieve lower R_DS(on), because they do not use a gate oxide and conduct current through a bulk SiC channel, eliminating surface channel resistance and oxide reliability constraints. This enables resistance values that are much closer to the theoretical unipolar limit than SiC MOSFETs, resulting in the lowest specific on‑resistance (R_DS(on)) per unit area among high‑voltage discrete devices.

Electrical advantages:

• Lower R_DS(on), per mm²:
  • SiC JFETs conduct through the bulk SiC material without a gate oxide, enabling the lowest specific on-resistance (RDS(A)) among high-voltage discrete devices and operation closer to the theoretical unipolar limit.
• No body diode and no reverse-recovery charge:
  • The absence of an intrinsic body diode eliminates reverse-recovery losses, reducing switching stress and improving efficiency, especially in protection and hot-swap applications.
• Integrated junction temperature sensing:
  • The JFET gate-source voltage can be forward-biased with a small current, allowing accurate on-chip junction temperature measurement without external sensors.

Reliability advantages

• No gate oxide, no oxide wear-out:
  • SiC JFETs eliminate gate-oxide reliability concerns such as threshold voltage drift and long-term degradation under high electric fields.
• Excellent robustness under surge and fault conditions:
  • SiC JFETs and SiC Combo JFETs are designed to operate safely in linear and quasi-linear mode during inrush, overload, and short-circuit events when used within their SOA.
• Positive temperature coefficient for easy paralleling:
  • Increasing on-resistance with temperature promotes stable current sharing when devices are connected in parallel, improving reliability at higher current levels.
• No mechanical wear:
  • As solid-state devices, SiC JFET-based solutions do not suffer from contact erosion or arcing, enabling repeated fault and hot-plug events without degradation.

System-level advantages

• Higher power density and smaller form factor:
  • Lower losses and reduced cooling requirements enable more compact designs, particularly in solid-state circuit breakers, eFuses, and hot-swap systems.
• Reduced external component count:
  • Integrated temperature sensing and controllable linear-mode behavior reduce the need for external sensors, shunt resistors, and protection components.
• Improved system efficiency and lower thermal management effort:
  • Lower conduction and switching losses translate directly into simpler thermal design and higher system efficiency.
• Enables new protection and control architectures:
  • Precise current limiting, fast interruption, and resettable protection enable solid-state circuit breakers, battery disconnects, and advanced hot-swap solutions that are difficult to implement with SiC MOSFETs alone.

A normally‑on SiC JFET becomes normally‑off by placing a low‑voltage silicon MOSFET in series with the JFET. When the MOSFET is off, its drain‑source voltage generates a negative gate‑source voltage on the JFET, pinching off the channel and blocking high voltage. This configuration is referred to as a cascode or Combo JFET, depending on implementation.

• Cascode JFET (CJFET): MOSFET and JFET are internally connected, behaving electrically like a MOSFET with ultra‑low R_DS(on), optimized for fast switch‑mode operation.
• Combo JFET: MOSFET and JFET gates are both accessible, allowing independent control, speed tuning, linear‑mode operation, current limiting, and safe paralleling.

Combo JFETs are therefore preferred for circuit protection, hot‑swap, and SSCB applications.

A Combo JFET integrates both dies in a single package, providing:

• Reduced PCB area (up to ~40% savings cited)
• Controlled parasitics and predictable switching
• Guaranteed avalanche coordination of the MOSFET
• Simplified qualification and higher reliability

This directly improves robustness in SSCB and hot‑swap designs.

Specific automotive‑grade SiC JFET and Combo JFET variants are AEC‑Q101 qualified. Qualification status is device‑specific and should be checked per OPN.

Yes. In Combo JFET configurations designed for normally‑off operation, loss of gate power forces the MOSFET off, which in turn applies a negative gate bias to the JFET, placing the device in a safe blocking state even under high voltage.

• MOSFET gate: typically 10–15 V (standard controller compatible)
• JFET gate (if driven): 0 V to +2 V for conduction, negative for turn‑off

This wide compatibility enables use with standard hot‑swap and eFuse controllers.

No inherent delay is introduced by the JFET. Switching speed is intentionally controllable via JFET gate resistance, enabling designers to slow switching for safe linear‑mode operation or speed it up for normal conduction.

SiC JFETs and Combo JFETs switch in the nanosecond range, but for circuit‑protection and hot‑swap applications they are typically intentionally slowed (μs–ms) to manage inrush current, SOA, and dv/dt stress safely.