Xilinx RFSoC Webinar Series

Session Timeout

Your session is about to expire. Do you want to extend the session?

00:

Extend My Session

Custom Meta Tags

Hero Banner

RFSoC Webinar Series

Intro Text

The advent of the inter-connected world brings innovations ranging from ubiquitous consumer broadband to ultra-low latency wireless vehicular communication and massive machine-type communications, all in constant pursuit of wider bandwidth and better signal fidelity. Meanwhile constraints on size, weight, power and programmability demand higher levels of integration within the system. Combining up to 16 channels of integrated multi-gigasample RF data converters with an Arm^® Cortex^®-A53 processing subsystem and UltraScale+ programmable logic, AMD Xilinx Zynq^® UltraScale+™ RFSoC takes center stage in this webinar series. Starting with an introduction to the RFSoC architecture and progressing towards system design with RF front-ends, you will learn practical design techniques including frequency-planning, multi-channel data converter synchronization, and advanced test and measurement solutions for 5G FR2 mmWave bands.

5G Solutions (RRCD)

5G Solutions

There has never been a better time to accelerate your 5G design journey. From infrastructure to endpoint, 5G will reach into every aspect of our business and personal lives.

Learn More

Frequency Planning in mmWave Applications with Xilinx Zynq UltraScale+ RFSoCs | Avnet Silica

Frequency Planning in mmWave Applications with Xilinx Zynq® UltraScale+™ RFSoCs

online, on-demand

With up to 16 channels of integrated RF-ADCs and RF-DACs in Xilinx Zynq® UltraScale+™ RFSoC devices, interfacing to mmWave RF up/down conversion requires careful frequency planning to ensure the best wideband performance. This webinar will present frequency planning guidelines and design considerations for mmWave transmit and receive chains. Our use case is applicable to a mmWave superheterodyne radio using Avnet’s mmWave Radio kit with Xilinx’s ZCU208, which features the Zynq UltraScale+ RFSoC Gen 3. You will learn a multi-step process to identify a suitable range of I/F frequencies based on target RF frequencies and maximum signal bandwidth. Performance refinements are then applied by considering harmonic products and image terms from both the RF-DACs and RF-ADCs and the RF signal chain.

Interconnecting the RF World with a Single Chip Radio Platform | Avnet Silica

RFSoC: Interconnecting the RF World with a Single Chip Radio Platform

online, on-demand

The modern world relies upon RF systems, with demands for these RF systems to be smaller, lower powered and higher performing, challenges which are often mutually exclusive. The Xilinx Zynq UltraScale+ RFSoC provides system developers with high performance capabilities thanks to its unique heterogeneous architecture and also addresses power and size challenges with RF-ADC and RF-DAC in the same die. Join this webinar to learn about RFSoC performance, target applications, how to retire project risk early on in the development cycle, and get an overview of available production solutions like system on modules.

Multi-Tile Synchronization Characterization and Performance on the Zynq UltraScale+ RFSoC Gen 3 | Avnet Silica

Multi-Tile Synchronization Characterization and Performance on the Zynq UltraScale+ RFSoC Gen 3

online, on-demand

Synchronizing data converters is critical for phased array and massive-MIMO applications, and effects like architecture, alignment, temperature, voltage and process can impact performance. In this webinar, we will review the Xilinx Zynq ® UltraScale+ ™ RFSoC data converter structure and recent multi-tile synchronization characterization and performance. A design methodology using HDL Coder ™ from MathWorks will be shown for custom implementations of multi-tile synchronization on the Xilinx ZCU208 evaluation kit.

Complementary Content

${loading}