Vision Projects with AMD-Xilinx MPSoCs
27 Oct 2022 - 28 Oct 2022
Winterthur, Switzerland
In this seminar the design of modern machine vision projects on AMD Zynq UltraScale+ devices will be illustrated. These devices are predestined for compute intensive vision algorithms as tasks can be outsourced to the programmable logic. Our partner Enclustra will highlight the advantages of the Zynq US+ devices on some real world projects. In the first session the partitioning of a design between hardware and software and the integration of custom video algorithms will be shown.
In the afternoon session we will show you how to connect MIPI CSI-2 camera modules to ZynqUS+ devices and use them within the Linux GStreamer framework. We will start from a simple "hello world" pipeline until a H.265 encoded network streaming application. In the final part a dual-camera design with an OnSemi Image Signal Processor and Images sensors will be presented.
All design files (Vivado + PetaLinux BSP) will be available for the attendees.
Dates & locations
- 27.10.2022. - Winterthur, Switzerland (exact venue to be announced)
Agenda
| Time |
Description |
| 8:45-9:00 |
Registration |
| 9:00-9:25 |
Welcome and introduction |
| 9:25-10:45 |
System Design in Vision Projects
- System Partitioning
- Managing System Complexity
- The Xilinx Tool-Flow on System Level
- Real-World Examples
|
| 10:45-11:00 |
Break & Table show |
| 11:00-12:00 |
Custom Video Algorithms in the FPGA
- Algorithm Acceleration
- Real-Time Overlay Rendering
- Low-Latency Frame Processing
|
| 12:00-13:00 |
Lunch |
| 13:00-14:30 |
From an Image Sensor to a GStreamer Video Pipeline
- Vivado reference design for the Enclustra Mercury+ XU8 SoM (Equipped with the AMD ZU7EV MPSoC)
- Introduction of the free Vitis Vision libraries
- PetaLinux
- Device Tree
- Video for Linux Drivers
- GStreamer live demos. From a simple video test pattern generator to H265 encoded network video streaming application
|
| 14:30-14:45 |
Break & Table show |
| 14:45-16:15 |
onsemi Image Signal Processor and Image Sensors
- Connecting the ISP & Image Sensor to a MPSoC. Explaining the Vivado Design for the Avnet Ultra96v2 Eval Kit equipped with the Dual Camera Mezzanine card
- Live Demo
|
| 16:15-16:45 |
Speech ZHAW Institute of Embedded Systems (InES) |
| 16:45-17:00 |
Summary, Discussions and Q&A |
| 17:00-17:30 |
Table show & meet the experts |
Registration closed
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Vision Projects with AMD-Xilinx MPSoCs | Avnet Silica
