Embedded Development with Vitis Unified IDE (for Adaptive SoCs [Zynq| Zynq Ultrascale+ MPSoC | Versal Adaptive SoC])

24 Sep 2025 - 24 Sep 2025

Germany, Jena

This seminar explores the complete journey from embedded hardware design to system-level integration on modern FPGAs and Adaptive SoCs. Through four in-depth sessions, we’ll cover cutting-edge tools, architectures, and techniques for unlocking the full potential of AMD’s adaptive computing platforms.

Agenda

• 8:45 AM - Greetings
• 9:00 AM - Session 1: Embedded Hardware for FPGAs and Adaptive SoCs
  • Motivation: Complex data processing challenges
  • Introduction: Adaptive SoC architecture
  • Softcores in FPGA Fabric: Microblaze™ flavours
  • Embedded hardware development in Vivado
• 10:30 AM - Coffee Break
• 11:00 AM - Session 2: Embedded Software Development
  • Vitis™ Unified IDE: Import the XSA and building the platform
  • Embedded Targets: Baremetal, OS support and libraries
  • Vitis™ Unified IDE: Setting up embedded applications
  • Extending designs into the PL fabric
• 12:30 AM - Lunch
• 1:30 PM - Session 3: System Level Design in Multicore Systems
  • APU and RPU Cluster and heterogenous scenarios
  • System Device Tree: SMP OS and Real Time OS
  • Debugging in multicore designs
  • Boot file generation
• 3:00 PM - Coffee Break
• 3:30 PM - Session 4: System Integration and HW Acceleration
  • Acceleration Principles and acceleration kernels
  • Vitis Library – reusable kernels
  • Revisit: Data processing design challenges
  • Outlook: AMD Versal™ adaptive SoC
• 5:00 PM - End

Location

GÖPEL electronic GmbH, Göschwitzer Straße 58/60, 07745 Jena, Deutschland

Registration

Registration is closed.