| Densities |
512Mb (LPSDR)
512Mb to 2Gb (LPDDR)
512Mb to 2Gb (LPDDR2)
8Gb to 32Gb (LPDDR3)
4Gb to i 28Gb (LPDDR4)
16Gb to 128Gb (LPDDR5) |
Provides flexibility for a variety of application designs. |
| Configurations |
xi 6, x32 (LPSDR, LPDDR)
xi 6, x32, x64 (LPDDR4)
x32, x64 (LPDDR3)
x32, (2 channels, x16) (LPDDR2)
x64 (4 channels, x16) (LPDDR4, LPDDR5) |
Enables the use of fewer components to support wide bus architectures. |
| Core Voltages |
Core Voltages 1.8V (LPSDR, LPDDR)
1.2V (LPDDR2, LPDDR3)
0.6V, 1.1V (LPDDR4)
0.5V, 1.05V (LPDDR5) |
Helps reduce power consumption-a key advantage over standard DRAM. |
| Clock Frequencies |
Up to 166 MHz (LPSDR)
Up to 208 MHz (LPDDR)
Up to 533 MHz (LPDDR2)
Up to 933 MHz (LPDDR3)
Up to 2133 MHz (LPDDR4)
Up to 3200 MHz (LPDDR5)
Up to 4250 MHz (LPDDR5x) |
Provides high performance, high bandwidth, and low power consumption. |
| Power Consumption |
Refer to specific data sheet |
Delivers low power consumption in standby and active modes, plus special mobile features to reduce power for a more efficient design. |
| Special Features |
Temperature-compensated self refresh (TCSR) |
Adjusts refresh timing to minimize power consumption at lower, ambient temperatures. |
| Partial-array self refresh (PASR) |
Reduces power by refreshing only critical data. |
| Deep power-down (DPD)' |
Provides an ultra-low power state when data retention is not required. |
| Programmable drive strength (OS) |
Enables adjustment for operation in point-to-point and point-to- 2-point applications. |
| Programmable V0H signal level (LPDDR4 only) |
Enables adjustment for operation in point-to-point and point-to- 2-point applications. |
| Temperature Ranges |
Temperature Ranges -3Q°C to +85°C 0NT LPDDR2/3/4/5)
-30°C to +105°C (XT LPDDR3/4)
-40°C to +85°C (IT)
-40°C to +95°C (IT LPDDR4, LPDDRS)
-40°C to +1OS°C (AT LPSDR, LPDDR, LPDDR2/4/5)
-40°C to +125°C (Ultra2 LPDDR2/4/5) |
Enables high performance in extreme environments |
| Packages |
PoP |
Saves board space by enabling a Mobile LPDRAM to be stacked on top of a processor so that the two components require only one foot print on the board. |
| Wafer |
Supports bare die with edge bond pads for easy stacking in SIP and MCP solutions. |
| FBGA |
Supports JEDEC-standard FBGA bailout. |
| Near memory package |
High density, smaller footprint. Excellent board-level reliability. Wide
10 for high bandwidth. Improved signal integrity with shorter distance between processor and memory. |
