Microchip Ethernet Transceivers (PHYs)
Microchip Ethernet PHYs are high-performance, small-footprint, low-power transceivers for electronics, automotive, industrial and enterprise applications
Microchip's 10/100/1000 Mbps Ethernet Physical Layer Transceivers (PHYs) are high-performance, small-footprint, low-power transceivers designed specifically for today's consumer electronics, automotive, industrial and enterprise applications. Available in the industry's smallest footprint and consuming up to 40% less power than similar products, they also have integrated voltage regulator and Electrostatic Discharge (ESD) protection components to help reduce your Bill of Material (BOM) costs. We offer 10BASE-T, 10BASE-T1S, 100BASE-TX, 100BASE-T1 and 1000BASE-T PHYs.
Microchip's 1–800 GbE PHYs target data center, service provider, enterprise and AI/ML applications. They provide retiming, gearboxing, a 2:1 hitless multiplexer (mux), crosspoint capabilities, optional AES-256 MACSec and IPSec encryption, port aggregation, nanosecond accuracy Precision Time Protocol (PTP) timestamping and Flexible Ethernet (FlexE) while operating over the industrial temperature range.
Featured products: Gigabit Ethernet PHYs for Time-Sensitive Networks
Microchip's LAN8840 and LAN8841 Gigabit Ethernet transceiver devices meet IEEE® 1588v2 standards for Precision Timing Protocol (PTP) to deliver critical process timing synchronization networks for industrial applications. Learn more about how these PHYs deliver IEEE 1588 time stamping for critical processes.
- LAN8840
- LAN8841
LAN8840 - Gbit Ethernet Transceiver with IEEE 1588 v2 support and RGMII
Supporting Precision Timing Protocol (PTP) Networks
The LAN8840 is a low-power, single-port triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver (PHY) that is optimized for precision process timing. The device enables highly accurate synchronization of motors, valves, actuators and sensors over standard CAT-5, CAT-5e and CAT-6, unshielded twisted pair (UTP) cables.
The LAN8840 supports industry-standard RGMII (Reduced Gigabit Media Independent Interface) providing chip-to-chip connection to a host device with an integrated Gigabit Ethernet MAC.
The LAN8840 provides high-accuracy IEEE 1588-2008 (v2) timestamping to support Microchip Time-Sensitive Network (TSN) Ethernet switches, as well as, SoCs and FPGAs supporting the RGMII interface. The LAN8840 also provides Synchronous Ethernet (SyncE), TSN frame preemption support and multiple power saving features.
Features
- Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications
- RGMII with 3.3V/2.5V/1.8V Tolerant I/Os
- RGMII Timing Supports On-Chip Delay According to RGMII Version 2.0, with Programming Options for External Delay and Making Adjustments and Corrections to TX and RX Timing Paths
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100/1000 Mbps) and Duplex (Half/Full)
- On-Chip Termination Resistors for the Differential Pairs
- On-Chip LDO Controller to Support Single 3.3V Supply Operation – Requires Only One External FET to Generate 1.1V for the Core
- Jumbo Frame Support Up to 16 KB
- 125 MHz Reference Clock Output
- Energy-Detect Power-Down Mode for Reduced Power Consumption When Cable is Not Attached
- EtherSynch® IEEE 1588v2/PTP
- Layer 2, UDP/IPv4 and UDP/IPv6 formats
- Tagged and non-tagged frame formats
- One-step and two-step modes of operation
- Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage for 100BASE-TX/1000BASE-T and Transmit Amplitude Reduction with 10BASE-Te Option
- Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection
- Programmable LED Outputs for Link, Activity, and Speed
- Baseline Wander Correction
- LinkMD® TDR-based Cable Diagnostic to Identify Faulty Copper Cabling
- Signal Quality Indication
- Parametric NAND Tree Support to Detect Faults Between Chip I/Os and Board
- Loopback Modes for Diagnostics
- Automatic MDI/MDI-X Crossover to Detect and Correct Pair Swap at All Speeds of Operation
- Automatic Detection and Correction of Pair Swaps, Pair Skew, and Pair Polarity
- MDC/MDIO Management Interface for PHY Register Configuration
- Interrupt Pin Option
- Power-Down and Power-Saving Modes
- Operating Voltages
- Core (VDD, VDDAL, VDDAL_PLL): 1.1V (External FET or Regulator)
- VDD I/O (VDDIO): 3.3V, 2.5V, or 1.8V
- Transceiver (VDDAH): 3.3V or 2.5V
- Available in commercial (0°C to +70°C) and extended industrial (-40°C to +105°C) temperature ranges
- 48-pin VQFN (7 mm × 7 mm) Package
LAN8841 - Gbit Ethernet Transceiver with IEEE 1588 v2 support and RGMII/GMII interface
Supporting Time Sensitive Networks (TSN)
The LAN8841 is a low-power, single-port triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver (PHY) that is optimized for precision process timing. The device enables highly accurate synchronization of motors, valves, actuators and sensors over standard CAT-5, CAT-5e and CAT-6, unshielded twisted pair (UTP) cables.
The LAN8841 provides RGMII (Reduced Gigabit Media Independent Interface) and GMII/MII (Gigabit Media Independent Interface/Media Independent Interface) for connection to Ethernet MACs in processors and switches for data transfer at 1000Mbps or 10/100Mbps.
The LAN8841 provides high-accuracy IEEE 1588-2008 (v2) timestamping to support Microchip Time-Sensitive Network (TSN) Ethernet switches, as well as, SoCs and FPGAs supporting the RGMII interface. The LAN8841 also provides Synchronous Ethernet (SyncE), TSN frame preemption support and multiple power saving features.
Features
- Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications
- GMII/MII Standard Interface with 3.3V/2.5V/1.8V Tolerant I/Os
- RGMII/GMII with 3.3V/2.5V/1.8V Tolerant I/Os
- RGMII Timing Supports On-Chip Delay According to RGMII Version 2.0, with Programming Options for External Delay and Making Adjustments and Corrections to TX and RX Timing Paths
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100/1000 Mbps) and Duplex (Half/Full)
- On-Chip Termination Resistors for the Differential Pairs
- 125 MHz Reference Clock Output
- Energy-Detect Power-Down Mode for Reduced Power Consumption When Cable is Not Attached
- EtherSynch® IEEE 1588v2/PTP
- Layer 2, UDP/IPv4 and UDP/IPv6 formats
- Tagged and non-tagged frame formats
- One-step and two-step modes of operation
- Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage for 100BASE-TX/1000BASE-T and Transmit Amplitude Reduction with 10BASE-Te Option
- Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection
- Five (5) Programmable LED Outputs for Link, Activity, and Speed
- Baseline Wander Correction
- LinkMD® TDR-based Cable Diagnostic to Identify Faulty Copper Cabling
- Signal Quality Indication
- Parametric NAND Tree Support to Detect Faults Between Chip I/Os and Board
- Loopback Modes for Diagnostics
- Automatic MDI/MDI-X Crossover to Detect and Correct Pair Swap at All Speeds of Operation • Automatic Detection and Correction of Pair Swaps, Pair Skew, and Pair Polarity
- MDC/MDIO Management Interface for PHY Register Configuration
- Interrupt Pin Option
- Power-Down and Power-Saving Modes
- Operating Voltages
- Core (VDD, VDDAL, VDDAL_PLL): 1.1V (External FET or Regulator)
- VDD I/O (VDDIO): 3.3V, 2.5V, or 1.8V
- Transceiver (VDDAH): 3.3V or 2.5V
- Available in commercial (0°C to +70°C) and extended industrial (-40°C to +105°C) temperature ranges
- 64-pin VQFN (8 mm × 8 mm) Package
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