NXP i.MX 8ULP

The i.MX 8ULP crossover applications processor family brings ultra-low power processing and advanced integrated security with EdgeLock® secure enclave to the intelligent edge.

Optimizing energy at the chip level is becoming increasingly crucial for designing energy-efficient edge systems. NXP’s innovative Energy Flex architecture implementation in i.MX 8ULP processors uniquely combines heterogeneous domain computing, design techniques and process technology. A dedicated power management subsystem offers more than 20 power mode combinations to deliver exceptional efficiency across a range of applications.

Building on our strong history of security solutions, NXP’s EdgeLock secure enclave is pre-configured to simplify complex security implementations for faster time to market and help designers avoid costly configuration errors.

The i.MX 8ULP family features up to two Arm® Cortex®-A35 running at 1 GHz, an Arm Cortex-M33 core, 3D/2D Graphics Processing Units (GPUs) and a Cadence® Tensilica® Hifi 4 DSP and Fusion DSP for low-power audio/voice and edge AI/ML processing.

i.MX 8 applications processors are part of NXP's EdgeVerse™ edge computing platform.

This page contains information on a preproduction product. Specifications and information here in are subject to change without notice.

Features

i.MX 8ULP Dual/Solo Applications Processors

• CPU
  • Up to two Arm® Cortex®-A35 @ 1.0 GHz
  • Arm Cortex-M33 @ 216 MHz
  • Cadence® Tensillica® Hifi 4 DSP @600 MHz for advanced audio, voice and ML processing and Fusion DSP @200 MHz for low-power voice and sensor hub processing
  • EdgeLockTM secure enclave
  • RISC-V powered Power Management Subsystem (µpower)
• Memory
  • 896 KB Total On Chip SRAM
• External Memory
  • LPDDR3/LPDDR4/LPDDR4X
  • SPI-NOR
  • SPI-NAND
• Graphics
  • 3D GPU includes: Open GL® ES 3.1, OpenCLTM, Vulkan®
  • 2D GPU
  • 1x MIPI DSI (4-lane) with PHY
    • Up-to 24-bit RGB (DBI/DPI)
  • Color EPD Display
• Connectivity
  • 10/100 Ethernet
  • FlexCAN
• Display/Camera
  • 1x MIPI CSI (2-lane) with PHY
• Packaging
  • FCBGA 9.4 X 9.4 mm2
  • MAPBGA 15 x 15 mm2
• Temperature Range
  • -40°C – 105°C

Block diagram

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