Renesas FemtoClock® Low-Phase-Noise Frequency Clock Synthesizers

Renesas FemtoClock®, FemtoClock Next Generation (NG), and FemtoClock 2 devices are advanced, high-performance clock-frequency synthesizers. Employing a simple, low-cost, fundamental-mode quartz crystal as the low frequency reference these devices synthesize high-quality, low-jitter clock signals with less than 0.5 ps of RMS phase noise, up to 1.3 GHz. The RC3 series also offers a jitter attenuation mode where it can take a noisy reference in and still provide 100fs jitter on its outputs.

FemtoClock devices are fully customizable, stand-alone solutions that generate reference frequencies allowing them to replace crystal and SAW oscillators in high-performance applications. This family of devices is often used to replace third overtone and high frequency fundamental (HFF, inverted mesa) crystal oscillators or expensive surface acoustic wave (SAW) oscillators. They are more reliable, cost less, and are more readily available with shorter lead times.

Unlike fixed frequency oscillators, FemtoClocks are a frequency-synthesis technology (clock synthesizer) capable of multiple clock frequencies and more flexibility in any application. Because FemtoClocks are silicon IC-based clock devices, additional clock tree functions unavailable in a single function fixed-frequency oscillator can be integrated into a single device. The Renesas FemtoClock family delivers a wide range of device packages and capabilities, starting with small 8-pin TSSOP devices that provide one clean, low jitter clock signal, and 4x4mm QFNs which provide 4 outputs. Also available are devices with more integrated functions, multiple outputs, multiple frequencies and other more complex programmable synthesis functions.

PAM4 technology is enabling a major leap in data transmission rates in both communications and data center segments. This impacts the performance requirements of the timing source in such systems. The Renesas high-performance family of Femtoclock 2 delivers superior jitter performance with low power in a very small form factor, enabling placement of the clock anywhere on the board at the point of use. This greatly simplifies the design by eliminating the additive jitter associated with the extensive clock routing on the board.

Beyond PAM4, Renesas FemtoClock timing solutions are ideal reference clocks for almost any jitter-sensitive application. They are designed to provide a reference clock to PHYs, switches, ASICs and network processors. The result is a simplified board design and layout, as well as improved time-to-market. Moreover, the FemtoClock family meets the low-jitter clock specification requirements of many interface standards, such as 10 Gigabit Ethernet, PCI Express®, Fibre Channel and SONET. While generally optimized for synthesizing reference clock frequencies commonly used in communication applications, there are also a variety of FemtoClock devices with frequencies useful for CPU, memory, logic and other general-purpose clocking applications, including ASICs, DSPs, CPUs and memory; communication (including SONET/SDH and SPI4.2); HDTV video; networking (including 1 Gb, 10 Gb,XAUI and 12 Gb Ethernet); PCI Express; SERDES and PHY reference clocks; serial storage (SAS, SATA, fibre channel 4, 8 and 10 Gb); and wireless infrastructure (including CPRI, RP3).

About Low-jitter Clocks

Jitter can be defined as the undesired deviation from an ideal periodic timing signal. Jitter may be observed in characteristics such as the frequency, phase, or amplitude of successive pulses. High levels of jitter can result in significant undesired system behavior in high-performance applications. Renesas offers the industry's leading portfolio of low-jitter clock synthesizers and phase-locked oscillators (PLL oscillators) to meet the needs of virtually any application.

Features

• Smallest <100fs clock generator and jitter attenuator available
• Very low jitter
  • 80 fs in CG mode
  • 100 fs in JA mode
• Very small footprint
  • 4x4 QFN is 1/3 the size of comp
  • Very few external components required
• Internal crystal options coming Q3

Benefits

• Competes with higher jitter devices by allowing shorter traces, so similar or better performance at the pin
• Can prevent major board re-work
• Failsafe design – so small you can put it in your design and if traces are clean enough you can take it out

Applications

• Wireline Infrastructure:
  • Switches, routers, line cards, timing cards
• Cloud servers / Data centers
• 5G Wireless infrastructure radio

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