New Product Introduction

Microchip LAN8770

Microchip’s LAN8770 is an IEEE® 802.3bw-compliant 100BASE-T1 Ethernet PHY

Microchip’s LAN8770 Ethernet PHY - product sample image

A ubiquitous Ethernet architecture simplifies the design, configuration, and control of many different applications. This is especially true for connected mobility that requires more high-speed data delivery than ever before. Automotive networks rely heavily on partial networking in which some segments are hibernated and woken up on demand. Microchip Technology Inc. (Nasdaq: MCHP), a leader in automotive Ethernet, today announced the LAN8770, an OPEN Alliance TC10 sleep standard Ethernet physical layer transceiver (PHY) with the industry’s lowest sleep current—less than 15 µA—which is around four times lower than other available devices.

SPE or Single pair Ethernet is a new Ethernet transceiver (PHY), Layers 2-7 remain the same. It is independent of speed; 10BASE T1, 100BASE T1, 1000BASE T1 and Reduces system cost, weight and complexity for wiring installations

The LAN8770 is a compact, cost-effective, single-port 100BASE-T1 Ethernet PHY compliant with the IEEE 802.3bw-2015 specification and available in a 5 x 5 mm or 6 x 6 mm wettable-flanks QFN package. The small package is ideal for space-constrained applications such as the infotainment head unit, telematics modules or Advanced Driver Assistance Systems (ADAS). It provides 100 Mbps transmit and receive capability over a single Unshielded Twisted Pair (UTP), exceeds automotive electromagnetic interference requirements and is Grade 1 (-40°C to +125°C) automotive AEC-Q100 qualified. In addition, the LAN8770 is Microchip Functional Safety Ready; it is specifically designed to simplify customers’ end-product ISO26262 safety certification with the support of specialized hardware safety features, Failure Modes, Effects, and Diagnostic Analysis (FMEDA) and safety manual.

 The LAN8770M and LAN8770R support communication with an Ethernet MAC via standard MII/RMII and MII/RMII/RGMII interfaces, respectively. An optional 125 MHz or 50 MHz reference clock output is also provided for RGMII and RMII applications, often enabling elimination of an external reference clock.

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