Placing greater intelligence at the edge

With the number of connected nodes that make up the Internet of Things (IoT) growing on a daily basis, it is universally accepted that the way in which machine learning (ML) inferencing is executed has to change. The need for real-time responsiveness means that laboriously transferring data back and forth will simply take too long, with decision making required in a much shorter timeframe. Another consideration is security, as this arrangement heightens the risk of cyberattacks.  

Consequently, a large proportion of data acquired by IoT node’s sensors will need to be processed at the source - rather than having all the work done in the cloud or at centralised data centre sites. Through this approach, secure, low latency operation can be delivered. 

By having the intelligence closer to where the action is, it will be possible for systems to react more quickly to changing situations, for instance, where there are serious cost implications or are safety critical, as well as allowing for better user experience without any annoying lags. Having access to edge-based ML inferencing will be beneficial in a broad array of application scenarios. Among these will be factory automation, machine monitoring, predictive maintenance, object recognition/categorisation, access control, and smart homes/buildings. 

Replacing centralised intelligence, to a certain degree, with a distributed strategy that puts more autonomy at the edge will call for locally situated processing capabilities. This is why microcontroller units (MCUs) are now starting to emerge that can provide the strong ML inferencing performance needed, while at the same time supporting low power operation.

Changing topologies

For cloud-based computing activities, there will generally be ample processing assets available, and the power being consumed is not usually perceived as a major problem. However, things are very different when such activities are going to be undertaken out at the network edge. Here, remotely situated IoT nodes will run off a battery supply - meaning that charge retention is essential in order that operational life can be extended for as long as possible. The processing capabilities incorporated into these nodes therefore need to balance high performance with minimal power consumption. Also, the large number of nodes forming a distributed IoT network make having cost-effective processing technology essential, to keep down the overall infrastructure investment.

Now available via Avnet Silica, NXP’s new MCX N Advanced MCUs are highly suited to addressing modern edge-based computing tasks. These devices, which are part of the semiconductor vendor’s expansive EdgeVerse™ edge computing platform, combine elevated performance with cores running at up to 150MHz, and strong security with an ultra-low power budget. By leveraging their on-chip accelerators, they can efficiently execute ML workloads. Supplied in 9mm x 9mm BGA footprint packages, they are compact enough to fit into even the most space limited IoT hardware. They also have a wide array of peripherals, which results in increased design versatility.

The devices in the MCX N Advanced series all feature an innovative multi-core processing architecture that is specifically targeted at intelligent edge implementations. Each of them has an on-chip neural processing unit (NPU) through which real-time ML inferencing can be conducted. Thanks to the NPU, ML tasks can be completed 30x quicker than using a conventional processing resource of equivalent size. With considerably shorter processing periods these MCUs do not have to stay awake for as long, meaning that there is less of a drain on their battery reserves. 

The basic MCU structure is comprised of a pair of Arm® Cortex®-M33 cores with 32-bit instruction sets, 2MB of integrated flash memory, a precision voltage reference and a real-time clock (RTC), plus data conversion elements with Four Single Ended 16-bit ADCs and different DAC options. The LP FlexComm interfacing technology featured here can be configured to act as an SPI, I²C or UART, as application requirements dictate. Furthermore, the EdgeLock^® secure subsystem assures protection against various forms of prospective attack. This provides a secure boot mechanism with an immutable root-of-trust (RoT) and hardware-accelerated cryptography, as well as both active and passive intrusion detection.  

The dual-core architecture of these MCUs is comprised of a full-featured Cortex-M33 core, which does all the heavy lifting, paired with a more streamlined M33 core, which is responsible for managing all the control functions. This arrangement means that operations can be conducted in parallel. 

The MCUs have an active current consumption about 45μA/MHz. In power-down mode, they draw less than 2.5μA, and under 1μA when in deep power-down mode. This makes them highly optimised for battery powered IoT usage. The MCUXpresso suite of software and development tools is available to help engineers with implementing these MCUs into their IoT hardware.

As part of this NXP MCU series, the MCX N94x family is aimed specifically at industrial use cases. It has numerous analogue peripherals included, such as built-in operational amplifier capabilities, two 12-bit DACs and one 14-bit DAC. Alongside these are Ethernet, CAN 2.0 and CAN-FD interfacing, plus motor control (BLDC/PMSM) support. In addition to its 2MB Flash memory, this device possesses 416kB of SRAM with error correction code (ECC). It also has CoolFlux DSP co-processing functionality.   

Complementing the MCX N94x family is the MCX N54x family, which is intended for consumer electronics and home automation related applications. Among its peripherals are high-speed USB connectivity, secure digital (SD) and smart card interfacing, plus 512kB of SRAM. It has a single 12-bit DAC included.

Concluding thoughts

The NXP MCX N Advanced series will enable ML workloads to be dealt with at the edge, thereby augmenting the effectiveness of deployed IoT infrastructure. This platform presents engineering teams with MCUs that facilitate design reuse, meaning that the objectives of successive development projects can be achieved without excessive allocation of time and effort. Also, through Avnet Silica’s technical advisers, comprehensive support is readily available.