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Taking advantage of an L1 cache, STM32H7 devices deliver the maximum theoretical performance of the Cortex-M7 core.

This is regardless whether code is executed from embedded Flash or external memory: 2020 CoreMark /856 DMIPS at 400 MHz fCPU.

AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
16 Kbytes +16 Kbytes of I-cache and D-cache
Up to 2 Mbytes of embedded dual-bank Flash memory, with ECC and Read-While-Write capability
A high-speed master direct memory access (MDMA) controller, two dual-port DMAs
Chrom-ART acceleration for efficient 2D image copy and double-precision FPU
Two USB OTG with dedicated power supply
Dual-mode Quad-SPI interface
Two FD-CAN controllers, a high-resolution timer
A TFT-LCD controller, a JPEG codec
Three fast 16-bit ADCs, two comparators and two operational amplifiers.
1 Mbyte of SRAM with a scattered architecture:192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 512 Kbytes, 288 Kbytes and 64 Kbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes
Power efficiency
The multi-power domains architecture allows the different power domains to be set in low-power mode to optimize the power efficiency. In addition to the main regulator featuring voltage scaling to supply the core in different voltage ranges during Run and Stop modes, the device also embeds a USB regulator to supply the embedded physical layer (PHY) and a backup regulator.
263 µ/MHz typical @VDD = 3.3 V and 25 °C in Run mode (peripherals off)
4 µA in Standby mode (low-power mode)