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Espressif security highlights

Espressif has made wafer-level changes to the ESP32 series of devices (ECO Version 3). These changes introduce major improvements for security.

These improvements include:

Secure Boot verification based on RSA with a pubic key up to 3072 bits
Flash encryption
Disabling JTAG debugging and UART boot

ESP32: Simplified flash encryption diagram

The keys used to ensure secure boot and encrypt the flash memory are stored in the one-time programmable (eFuse) on-chip memory. Once programmed, the eFuse memory can be configured to be inaccessible to any software running on the device; only the hardware on the device can read the keys.

The eFuse also controls the JTAG and UART security features. Once disabled via the OTP eFuse, the features cannot be re-enabled.

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Infineon Secure MCU and element

The Secure Enclave technology from Infineon can be found in its Optiga Trust M secure solution, with tamper-resistant hardware that is certified to Common Criteria EAL6+. It can be used alongside any MCU, MPU or application processor, and operates autonomously. The Optiga Trust M features include:

Common Criteria EAL6+ certification
ECC NIST curves up to P-512
RSA up to 2048
AES up to 256, HMAC up to SHA-512
TRNG
TLS v1.2 PRF and HKDF up to SHA-512

Infineon’s secure enclave technology can also be found in the PSOC Edge family of MCUs with hardware-assisted Machine Learning acceleration.

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Microchip Secure PIC32

Microchip offers some of the industry’s most scalable security features available today. These features are backed up by Microchip’s hardware, software, tools and functions for implementing effective protection at the embedded level.

The security features available include:

Symmetric and Asymmetric Cryptography (secret and public key)
Integrity check monitors
Hardware Root of Trust (secure boot)
Secure firmware update (secure bootloader)
TRNG
Tamper detection
Secure key storage
And much more…

Click to enlarge image

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NXP Secure MCU and Secure element solutions

The NXP EdgeLock secure elements (SE) and secure authenticators (SA) have been developed to provide edge-to-cloud security by supporting a Root of Trust at the chip level. EdgeLock Secure Enclave is a standard feature in the i.MX 8ULP and i.MX 9 application processors.

EdgeLock is an on-chip, self-contained subsystem with its own dedicated security core, ROM, and secure RAM. It can provide security features to the other processing cores on an SoC. This physically isolated architecture creates a secure perimeter around the other parts of the SoC, making secure key store management, cryptography and other security features simpler to implement.

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Renesas RA Family with Secure Crypto engines

Renesas approaches security at the chip-level. Building security into the MCU provides an inseparable hardware Root of Trust.

The security features in the Renesas devices includes:

Integrated secure element functionality
Tamper resistance
Unlimited secure key storage
Hardware cryptographic acceleration
SPA/DPA resistance
Isolation technologies including Arm TrustZone
Device lifecycle management

Security runs through the Renesas product line, including:

RA Family of MCUs
RX Family of MCUs and RX Security Solutions
RZ Family of MPUs
Renesas Synergy platform

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STMicroelectronics scalable security on MCU

ST’s STM32Trust offers a Trusted Execution Environment (TEE) on many of its MCUs. STM32Trust is built on the four pillars of secure hardware, Root of Trust, certifications & regulations, and software & services.

STM32Trust supports SESIP (Security Evaluation Standard for IoT Platforms, from the consensus-driven technical standards organization, GlobalPlatform), and the Platform Security Architecture (PSA).

Many of ST’s MCUs and the STM32 MPUs are PSA Certified Level 1, PSA Certified Level 3, or SESIP certified. TEE is a family of certified security services, developed and maintained by ST.